JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847

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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar#103847
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@TIHanTIHan commented Jun 22, 2024

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Contributes to #99957

Adds:

  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar

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Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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TIHan marked this pull request as ready for review June 22, 2024 04:14
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TIHan commented Jun 22, 2024•
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@dotnet/arm64-contrib @kunalspathak this is ready.

Example codegen:

  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr

Stress tests all passed:

===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

TIHan
TIHan commented Jun 22, 2024
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp Outdated
@kunalspathakkunalspathak added the arm-sve Work related to arm64 SVE/SVE2 support label Jun 22, 2024
This was referenced Jun 22, 2024
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@TIHan

TIHan commented Jun 24, 2024•
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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.

kunalspathak
kunalspathak suggested changes Jun 25, 2024
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We should add ConditionalSelect tests for Extract*Vector API.

Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template Outdated
Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template Outdated
Comment threadsrc/coreclr/jit/lowerarmarch.cpp
Comment threadsrc/coreclr/jit/hwintrinsic.h Outdated
Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp Outdated
This was referenced Jun 25, 2024
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@TIHan

TIHan commented Jun 26, 2024•
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0

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kunalspathak commented Jun 26, 2024

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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0

are you still blocked on this or is the PR working as expected?

@TIHan

TIHan commented Jun 27, 2024

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are you still blocked on this or is the PR working as expected?

I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).

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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

This was referenced Jun 27, 2024
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tannergooding
tannergooding reviewed Jun 28, 2024
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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
/// LASTA Wresult, Pg, Zop.B
/// LASTA Bresult, Pg, Zop.B
/// </summary>
public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);

@tannergoodingtannergoodingJun 28, 2024

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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).

These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:

publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)

These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.

The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.

So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic

@tannergoodingtannergoodingJun 28, 2024•
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-- The names I gave above maybe aren't the best.

The concepts involved is we have what is logically similar to:

  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)

There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement

So the natural way to combine them would maybe instead be:

TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);

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Not super happy with ExtractVector* though since it's not actually extracting a vector

It's extracting a scalar and simply storing it in element 0 of a destination vector register

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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))

That gives us a single understandable name and lets us generate the vector form where its appropriate still.

@TIHan

TIHan commented Jul 1, 2024

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We are skipping these APIs for now.

@TIHanTIHan added the NO-MERGE The PR is not ready for merge yet (see discussion for detailed reasons) label Jul 1, 2024
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kunalspathak commented Jul 2, 2024

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@TIHan - can we close this, since we will have to rewrite part of it anyway?

@TIHanTIHan closed this Jul 2, 2024
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847
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Contributes to #99957
Adds:
  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar
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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Tagging subscribers to this area: @dotnet/area-system-runtime-intrinsics

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June 22, 2024 04:14
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@dotnet/arm64-contrib @kunalspathak this is ready.
Example codegen:
  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
Stress tests all passed:
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

TIHan
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.
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We should add ConditionalSelect tests for Extract*Vector API.
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
Comment threadsrc/coreclr/jit/hwintrinsic.h
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Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
are you still blocked on this or is the PR working as expected?
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are you still blocked on this or is the PR working as expected?
I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).
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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

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tannergooding
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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
 /// LASTA Wresult, Pg, Zop.B
 /// LASTA Bresult, Pg, Zop.B
 /// </summary>
 public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);
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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).
These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:
publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)
These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.
The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.
So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic
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-- The names I gave above maybe aren't the best.
The concepts involved is we have what is logically similar to:
  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)
There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement
So the natural way to combine them would maybe instead be:
TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);
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Not super happy with ExtractVector* though since it's not actually extracting a vector
It's extracting a scalar and simply storing it in element 0 of a destination vector register
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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))
That gives us a single understandable name and lets us generate the vector form where its appropriate still.
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We are skipping these APIs for now.
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@TIHan - can we close this, since we will have to rewrite part of it anyway?
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar#103847
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Contributes to #99957
Adds:
  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar
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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Tagging subscribers to this area: @dotnet/area-system-runtime-intrinsics

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@dotnet/arm64-contrib @kunalspathak this is ready.
Example codegen:
  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
Stress tests all passed:
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.
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We should add ConditionalSelect tests for Extract*Vector API.
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
are you still blocked on this or is the PR working as expected?
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are you still blocked on this or is the PR working as expected?
I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).
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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
 /// LASTA Wresult, Pg, Zop.B
 /// LASTA Bresult, Pg, Zop.B
 /// </summary>
 public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);
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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).
These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:
publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)
These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.
The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.
So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic
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-- The names I gave above maybe aren't the best.
The concepts involved is we have what is logically similar to:
  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)
There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement
So the natural way to combine them would maybe instead be:
TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);
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Not super happy with ExtractVector* though since it's not actually extracting a vector
It's extracting a scalar and simply storing it in element 0 of a destination vector register
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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))
That gives us a single understandable name and lets us generate the vector form where its appropriate still.
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We are skipping these APIs for now.
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@TIHan - can we close this, since we will have to rewrite part of it anyway?
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar#103847
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Contributes to #99957
Adds:
  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar
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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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@dotnet/arm64-contrib @kunalspathak this is ready.
Example codegen:
  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
Stress tests all passed:
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.
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We should add ConditionalSelect tests for Extract*Vector API.
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
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Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
are you still blocked on this or is the PR working as expected?
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are you still blocked on this or is the PR working as expected?
I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).
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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
 /// LASTA Wresult, Pg, Zop.B
 /// LASTA Bresult, Pg, Zop.B
 /// </summary>
 public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);
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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).
These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:
publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)
These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.
The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.
So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic
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-- The names I gave above maybe aren't the best.
The concepts involved is we have what is logically similar to:
  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)
There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement
So the natural way to combine them would maybe instead be:
TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);
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Not super happy with ExtractVector* though since it's not actually extracting a vector
It's extracting a scalar and simply storing it in element 0 of a destination vector register
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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))
That gives us a single understandable name and lets us generate the vector form where its appropriate still.
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We are skipping these APIs for now.
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@TIHan - can we close this, since we will have to rewrite part of it anyway?
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847
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Contributes to #99957
Adds:
  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar
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This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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@dotnet/arm64-contrib @kunalspathak this is ready.
Example codegen:
  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
Stress tests all passed:
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.
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We should add ConditionalSelect tests for Extract*Vector API.
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
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Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
are you still blocked on this or is the PR working as expected?
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are you still blocked on this or is the PR working as expected?
I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).
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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
 /// LASTA Wresult, Pg, Zop.B
 /// LASTA Bresult, Pg, Zop.B
 /// </summary>
 public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);
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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).
These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:
publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)
These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.
The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.
So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic
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-- The names I gave above maybe aren't the best.
The concepts involved is we have what is logically similar to:
  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)
There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement
So the natural way to combine them would maybe instead be:
TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);
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Not super happy with ExtractVector* though since it's not actually extracting a vector
It's extracting a scalar and simply storing it in element 0 of a destination vector register
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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))
That gives us a single understandable name and lets us generate the vector form where its appropriate still.
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We are skipping these APIs for now.
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@TIHan - can we close this, since we will have to rewrite part of it anyway?
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar#103847
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Contributes to #99957
Adds:
  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar
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@dotnet/arm64-contrib @kunalspathak this is ready.
Example codegen:
  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
Stress tests all passed:
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

TIHan
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.
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We should add ConditionalSelect tests for Extract*Vector API.
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
Comment threadsrc/coreclr/jit/hwintrinsic.h
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Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
are you still blocked on this or is the PR working as expected?
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are you still blocked on this or is the PR working as expected?
I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).
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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
 /// LASTA Wresult, Pg, Zop.B
 /// LASTA Bresult, Pg, Zop.B
 /// </summary>
 public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);
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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).
These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:
publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)
These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.
The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.
So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic
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-- The names I gave above maybe aren't the best.
The concepts involved is we have what is logically similar to:
  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)
There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement
So the natural way to combine them would maybe instead be:
TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);
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Not super happy with ExtractVector* though since it's not actually extracting a vector
It's extracting a scalar and simply storing it in element 0 of a destination vector register
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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))
That gives us a single understandable name and lets us generate the vector form where its appropriate still.
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We are skipping these APIs for now.
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@TIHan - can we close this, since we will have to rewrite part of it anyway?
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar#103847
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Contributes to #99957
Adds:
  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar
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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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@dotnet/arm64-contrib @kunalspathak this is ready.
Example codegen:
  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
Stress tests all passed:
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

TIHan
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.
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We should add ConditionalSelect tests for Extract*Vector API.
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
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Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
are you still blocked on this or is the PR working as expected?
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are you still blocked on this or is the PR working as expected?
I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).
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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
 /// LASTA Wresult, Pg, Zop.B
 /// LASTA Bresult, Pg, Zop.B
 /// </summary>
 public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);
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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).
These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:
publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)
These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.
The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.
So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic
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-- The names I gave above maybe aren't the best.
The concepts involved is we have what is logically similar to:
  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)
There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement
So the natural way to combine them would maybe instead be:
TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);
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Not super happy with ExtractVector* though since it's not actually extracting a vector
It's extracting a scalar and simply storing it in element 0 of a destination vector register
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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))
That gives us a single understandable name and lets us generate the vector form where its appropriate still.
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We are skipping these APIs for now.
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@TIHan - can we close this, since we will have to rewrite part of it anyway?
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar - #103847
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JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar#103847
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Contributes to #99957
Adds:
  • ExtractLastVector
  • ExtractLastScalar
  • ExtractAfterLastVector
  • ExtractAfterLastScalar
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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Note regarding the new-api-needs-documentation label:
This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Tagging subscribers to this area: @dotnet/area-system-runtime-intrinsics

See info in area-owners.md if you want to be subscribed.
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@dotnet/arm64-contrib @kunalspathak this is ready.
Example codegen:
  • ExtractLastScalar for int
G_M47661_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M47661_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 9.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lasta w0, p0, z16.sG_M47661_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastScalar for double
IN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M12491_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.dIN0005: 000020 lasta z0, p0, z16.dG_M12491_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
  • ExtractLastVector for int
G_M39689_IG01: ; func=00, offs=0x000000, size=0x0010, bbWeight=1, PerfScore 3.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IGIN0006: 000000 stp fp, lr,[sp, #-0x20]!IN0007: 000004mov fp,spIN0008: 000008str xzr,[fp, #0x10] // [V00 loc0]IN0009: 00000C str xzr,[fp, #0x18] // [V00 loc0+0x08]G_M39689_IG02: ; offs=0x000010, size=0x0014, bbWeight=1, PerfScore 7.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0001], byrefIN0001: 000010 movi v16.4s, #0IN0002: 000014str q16,[fp, #0x10] // [V00 loc0]IN0003: 000018 ldr q16,[fp, #0x10] // [V00 loc0]IN0004: 00001C ptrue p0.sIN0005: 000020 lastb z0, p0, z16.sG_M39689_IG03: ; offs=0x000024, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extendIN000a: 000024 ldp fp, lr,[sp], #0x20IN000b: 000028ret lr
Stress tests all passed:
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractLastScalar_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastVector_UInt64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Byte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Double() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Int64() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_SByte() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_Single() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt16() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt32() : 7
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.SveExtractAfterLastScalar_UInt64() : 7
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

TIHan
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Jun 22, 2024
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
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@kunalspathak this is ready again. Hope this is a reasonable compromise. I didn't create a flag, but I created a function. There isn't any room for an additional flag.
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We should add ConditionalSelect tests for Extract*Vector API.
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
Comment threadsrc/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
Comment threadsrc/tests/JIT/HardwareIntrinsics/Arm/Shared/SveExtractTest.template
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Comment threadsrc/coreclr/jit/lowerarmarch.cpp
Comment threadsrc/coreclr/jit/hwintrinsic.h
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Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
Comment threadsrc/coreclr/jit/hwintrinsiccodegenarm64.cpp
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
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@kunalspathak this is almost done, but I'm having issues with the ConditionalSelectScenarios when TieredCompilation=0
are you still blocked on this or is the PR working as expected?
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are you still blocked on this or is the PR working as expected?
I'm making progress, basically we can't remove the sel instruction for ConditionalSelect(mask, ExtractLastVector, falseOp) and ConditionalSelect(mask, ExtractAfterLastVector, falseOp).
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@kunalspathak this is ready, apart from some ConditionalSelect issues that we are trying to address.

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tannergooding
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Jun 28, 2024
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Comment threadsrc/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
 /// LASTA Wresult, Pg, Zop.B
 /// LASTA Bresult, Pg, Zop.B
 /// </summary>
 public static unsafe byte ExtractAfterLastScalar(Vector<byte> value) => ExtractAfterLastScalar(value);
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The issue is that the managed signature of these APIs isn't correct (and wasn't caught in API review).
These all behave specially and need to take a mask explicitly, so should've been in a general shape that looked more like:
publicstaticTExtractAfterLastActiveToScalar(Vector<T>mask,Vector<T>value)publicstaticVector<T>ExtractAfterLastActiveToVector(Vector<T>mask,Vector<T>value)
These are shipping as experimental in .NET 9, so we can go ahead and fix it now and follow up in API review later, but we should log an issue tracking that.
The general consideration is that LASTA and LASTB take a destination register, mask register, and input register. The mask is used to determine which input element is being extracted, so for LASTA (extract after last) it finds the index of the last element in mask that is "active" (all bits set) and extracts index+1 from value. In the case that the mask is zero or allbitsset, it uses index 0. While for LASTB (extract last) it finds the index of the last element in mask that is "active" (all bits set) and extracts that index from value. In the case that mask is zero or allbitsset, it uses the last index.
So, the signatures must explicitly take a mask and they shouldn't participate in the general EmbeddedMaskOperation containment logic
@tannergoodingtannergoodingJun 28, 2024•

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-- The names I gave above maybe aren't the best.
The concepts involved is we have what is logically similar to:
  • T Extract(Vector<T> vector, int index)
  • Vector<T> ExtractVector(Vector<T> vector, int index)
There's then a modifier on top which in other APIs is exposed as LastActiveElement and AfterLastActiveElement
So the natural way to combine them would maybe instead be:
TExtractAfterLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorAfterLastActiveElement(Vector<T>mask,Vector<T>vector);TExtractLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorLastActiveElement(Vector<T>mask,Vector<T>vector);// or possiblyTExtractFromLastActiveElement(Vector<T>mask,Vector<T>vector);Vector<T>ExtractVectorFromLastActiveElement(Vector<T>mask,Vector<T>vector);
@tannergoodingtannergoodingJun 28, 2024

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Not super happy with ExtractVector* though since it's not actually extracting a vector
It's extracting a scalar and simply storing it in element 0 of a destination vector register
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Give that the vector form always zero extends and there isn't a great name for it, we could support it by recognizing CreateScalar(ExtractFromLastActiveElement(mask, vector))
That gives us a single understandable name and lets us generate the vector form where its appropriate still.
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We are skipping these APIs for now.
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@TIHan - can we close this, since we will have to rewrite part of it anyway?
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