Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo:mul-long-arm64
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Optimize Vector128<long> multiplication for arm64#104177
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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset

neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo merged 8 commits into
dotnet:mainfrom
EgorBo:mul-long-arm64
Jul 2, 2024
Merged

Optimize Vector128<long> multiplication for arm64#104177
EgorBo merged 8 commits into
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EgorBo:mul-long-arm64

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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset

neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo merged 8 commits into
dotnet:mainfrom
EgorBo:mul-long-arm64
Jul 2, 2024
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Optimize Vector128<long> multiplication for arm64#104177
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EgorBo:mul-long-arm64

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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset

neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo merged 8 commits into
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EgorBo:mul-long-arm64
Jul 2, 2024
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Optimize Vector128<long> multiplication for arm64#104177
EgorBo merged 8 commits into
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EgorBo:mul-long-arm64

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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset

neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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, 'i'); if (__m === '*' || __re.test(location.href)) { injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links"); } } catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); } })(); (function(){ try { var __m = "youtube.com"; var __re = new RegExp('^' + "youtube\\.com" + '
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Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo:mul-long-arm64
Jul 2, 2024
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Optimize Vector128<long> multiplication for arm64#104177
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EgorBo:mul-long-arm64

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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

@EgorBot

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset

neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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, 'i'); if (__m === '*' || __re.test(location.href)) { injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default"); } } catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); } })(); (function(){ try { var __m = "*"; var __re = new RegExp('^' + ".*" + '
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Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo merged 8 commits into
dotnet:mainfrom
EgorBo:mul-long-arm64
Jul 2, 2024
Merged

Optimize Vector128<long> multiplication for arm64#104177
EgorBo merged 8 commits into
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EgorBo:mul-long-arm64

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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset

neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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, 'i'); if (__m === '*' || __re.test(location.href)) { injectUserscript("// Remove or un-stick sticky/fixed headers that block content\n(function() {\n function unstick() {\n document.querySelectorAll('header, nav, [role=\"banner\"], .header, .navbar, .sticky, .fixed-top, [style*=\"position: fixed\"], [style*=\"position:sticky\"]').forEach(function(el) {\n if (el.style.position === 'fixed' || el.style.position === 'sticky' || \n getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {\n el.style.position = 'static';\n el.style.top = 'auto';\n el.style.zIndex = 'auto';\n }\n });\n }\n \n unstick();\n \n var observer = new MutationObserver(unstick);\n observer.observe(document.body, { childList: true, subtree: true, attributes: true, attributeFilter: ['style', 'class'] });\n})();", "Kill Sticky Headers"); } } catch(__e) { console.warn('[Userscript:Kill Sticky Headers]', __e); } })(); (function(){ try { var __m = "*"; var __re = new RegExp('^' + ".*" + '
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Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo merged 8 commits into
dotnet:mainfrom
EgorBo:mul-long-arm64
Jul 2, 2024
Merged

Optimize Vector128<long> multiplication for arm64#104177
EgorBo merged 8 commits into
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EgorBo:mul-long-arm64

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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

@EgorBot

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset

neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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Optimize Vector128<long> multiplication for arm64 - #104177

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EgorBo merged 8 commits into
dotnet:mainfrom
EgorBo:mul-long-arm64
Jul 2, 2024
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Optimize Vector128<long> multiplication for arm64#104177
EgorBo merged 8 commits into
dotnet:mainfrom
EgorBo:mul-long-arm64

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Follow up to #103555 for arm64

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
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@EgorBot -arm64 -profiler

usingSystem.IO.Hashing;usingBenchmarkDotNet.Attributes;publicclassBench{staticreadonlybyte[]Data=newbyte[1000000];[Benchmark]publicbyte[]BenchXxHash128(){XxHash128hash=new();hash.Append(Data);returnhash.GetHashAndReset();}}

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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Comment threadsrc/coreclr/jit/hwintrinsicarm64.cpp Outdated
Comment on lines +21932 to +21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}

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Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

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Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
MethodToolchainMeanErrorRatio
BenchXxHash128Main116.9 μs0.05 μs1.00
BenchXxHash128PR109.8 μs0.04 μs0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

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neon-sunset commented Jul 1, 2024

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I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment threadsrc/coreclr/jit/gentree.cpp Outdated
Comment on lines +22005 to +22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);

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nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

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Thanks! Applied

@EgorBo
EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo
EgorBo merged commit 6e039a8 into dotnet:mainJul 2, 2024
@EgorBo
EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);

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Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

@EgorBoEgorBoJul 2, 2024

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@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

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Ah, that makes sense, 👍

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