[RISC-V] Use auipc for code addresses in INS_OPTS_{RL,RC,JALR} by tomeksowi · Pull Request #116780 · dotnet/runtime

tomeksowi · 2025-06-18T10:21:21Z

Make code segment addresses (for jumps, branches, data-constants, labels, etc) PC-relative for INS_OPTS_{RL,RC,JALR}.

Since the code size is limited to about 2 Gb ¹, a canonical auipc + I-type instruction combo with 32-bit range should reach anywhere. Treating code addresses as absolute even if known at compile-time is counter-effective because RISC-V needed to emit "myriad sequences" (more instructions) to synthesize long constants. It also simplifies the emitter.

Part of #84834, cc @dotnet/samsung

See this discussion. If we ever hit such failures, either the absolute addressing paths can be brought back, or some other solution like branch islands can be worked out. Either way, code sizes >2 Gb aren't likely, assuming them as default complicates the output asm. ↩

dotnet-policy-service · 2025-06-18T10:22:09Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

risc-vv · 2025-06-18T10:26:04Z

RISC-V Release-CLR-VF2: 9084 / 9114 (99.67%)

=======================
passed: 9084
failed: 2
skipped: 599
killed: 28
------------------------
TOTAL tests: 9713
VIRTUAL time: 11h 2min 1s 64ms
REAL time: 45min 14s 333ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-QEMU: 9083 / 9113 (99.67%)

=======================
passed: 9083
failed: 2
skipped: 599
killed: 28
------------------------
TOTAL tests: 9712
VIRTUAL time: 35h 16min 47s 966ms
REAL time: 36min 5s 33ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-VF2: 306856 / 308579 (99.44%)

=======================
passed: 306856
failed: 1712
skipped: 39
killed: 11
------------------------
TOTAL tests: 308618
VIRTUAL time: 20h 44min 50s 168ms
REAL time: 2h 10min 49s 664ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-QEMU: 274559 / 275631 (99.61%)

=======================
passed: 274559
failed: 1064
skipped: 39
killed: 8
------------------------
TOTAL tests: 275670
VIRTUAL time: 31h 41min 43s 491ms
REAL time: 1h 11min 0s 282ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: fc376f2208cbc3c3ec10b4803756ef452a83527c
CI: 3679e38be10e43c36a92b0f56774af3dfa4facf2
REPO: tomeksowi/runtime
BRANCH: emit-auipc
CONFIG: Release
LIB_CONFIG: Release

tomeksowi · 2025-06-18T10:51:57Z

No regressions. Diffs on bigger corpus coming soon.

Diffs are based on 12,289 contexts (10,113 MinOpts, 2,176 FullOpts).

Overall (-9,576 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
test.mch	6,320,024	-9,576	-0.50%

MinOpts (-6,616 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
test.mch	4,850,460	-6,616	-0.43%

FullOpts (-2,960 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
test.mch	1,469,564	-2,960	-0.64%

Example diffs

test.mch

-12 (-9.68%) : 9004.dasm - Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.BinaryExpressionSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)

@@ -28,19 +28,16 @@ G_M16219_IG02: ; bbWeight=1, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byre
addi ra, zero, 0xD1FFAB1E
bltu ra, t6, G_M16219_IG07
zext.w a1, a1
- auipc t6, 0xD1FFAB1E- addi a2, t6, 0xD1FFAB1E+ auipc a2, 0xD1FFAB1E+ addi a2, a2, 0xD1FFAB1E
slli a3, a1, 2
add a2, a2, a3
lw a2, 0xD1FFAB1E(a2)
- lui t6, 0xD1FFAB1E- addi t6, t6, 0xD1FFAB1E- lui a3, 0xD1FFAB1E- slli a3, a3, 20- add a3, a3, t6+ auipc a3, 0xD1FFAB1E+ addi a3, a3, 0xD1FFAB1E
add a2, a2, a3
jr a2
- ;; size=64 bbWeight=1 PerfScore 19.00+ ;; size=52 bbWeight=1 PerfScore 14.00
G_M16219_IG03: ; bbWeight=0.50, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byref
ld a0, 0xD1FFAB1E(a0)
;; size=4 bbWeight=0.50 PerfScore 1.00
@@ -68,7 +65,7 @@ RWD00 dd	G_M16219_IG03 - G_M16219_IG02
dd	G_M16219_IG05 - G_M16219_IG02
-; Total bytes of code 124, prolog size 16, PerfScore 38.25, instruction count 26, allocated bytes for code 124 (MethodHash=9308c0a4) for method Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.BinaryExpressionSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)+; Total bytes of code 112, prolog size 16, PerfScore 33.25, instruction count 26, allocated bytes for code 112 (MethodHash=9308c0a4) for method Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.BinaryExpressionSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)
; ============================================================
Unwind Info:
@@ -79,7 +76,7 @@ Unwind Info:
E bit : 0
X bit : 0
Vers : 0
- Function Length : 31 (0x0001f) Actual length = 124 (0x00007c)+ Function Length : 28 (0x0001c) Actual length = 112 (0x000070)
---- Epilog scopes ----
---- Scope 0
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

-12 (-9.09%) : 9477.dasm - Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.BlockSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)

@@ -28,19 +28,16 @@ G_M31535_IG02: ; bbWeight=1, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byre
addi ra, zero, 0xD1FFAB1E
bltu ra, t6, G_M31535_IG08
zext.w a1, a1
- auipc t6, 0xD1FFAB1E- addi a2, t6, 0xD1FFAB1E+ auipc a2, 0xD1FFAB1E+ addi a2, a2, 0xD1FFAB1E
slli a3, a1, 2
add a2, a2, a3
lw a2, 0xD1FFAB1E(a2)
- lui t6, 0xD1FFAB1E- addi t6, t6, 0xD1FFAB1E- lui a3, 0xD1FFAB1E- slli a3, a3, 20- add a3, a3, t6+ auipc a3, 0xD1FFAB1E+ addi a3, a3, 0xD1FFAB1E
add a2, a2, a3
jr a2
- ;; size=64 bbWeight=1 PerfScore 19.00+ ;; size=52 bbWeight=1 PerfScore 14.00
G_M31535_IG03: ; bbWeight=0.56, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byref
ld a0, 0xD1FFAB1E(a0)
;; size=4 bbWeight=0.56 PerfScore 1.11
@@ -73,7 +70,7 @@ RWD00 dd	G_M31535_IG03 - G_M31535_IG02
dd	G_M31535_IG05 - G_M31535_IG02
-; Total bytes of code 132, prolog size 16, PerfScore 38.17, instruction count 28, allocated bytes for code 132 (MethodHash=959684d0) for method Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.BlockSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)+; Total bytes of code 120, prolog size 16, PerfScore 33.17, instruction count 28, allocated bytes for code 120 (MethodHash=959684d0) for method Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.BlockSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)
; ============================================================
Unwind Info:
@@ -84,7 +81,7 @@ Unwind Info:
E bit : 0
X bit : 0
Vers : 0
- Function Length : 33 (0x00021) Actual length = 132 (0x000084)+ Function Length : 30 (0x0001e) Actual length = 120 (0x000078)
---- Epilog scopes ----
---- Scope 0
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

-12 (-8.57%) : 1988.dasm - Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.CompilationUnitSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)

@@ -28,19 +28,16 @@ G_M20649_IG02: ; bbWeight=1, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byre
addi ra, zero, 0xD1FFAB1E
bltu ra, t6, G_M20649_IG09
zext.w a1, a1
- auipc t6, 0xD1FFAB1E- addi a2, t6, 0xD1FFAB1E+ auipc a2, 0xD1FFAB1E+ addi a2, a2, 0xD1FFAB1E
slli a3, a1, 2
add a2, a2, a3
lw a2, 0xD1FFAB1E(a2)
- lui t6, 0xD1FFAB1E- addi t6, t6, 0xD1FFAB1E- lui a3, 0xD1FFAB1E- slli a3, a3, 20- add a3, a3, t6+ auipc a3, 0xD1FFAB1E+ addi a3, a3, 0xD1FFAB1E
add a2, a2, a3
jr a2
- ;; size=64 bbWeight=1 PerfScore 19.00+ ;; size=52 bbWeight=1 PerfScore 14.00
G_M20649_IG03: ; bbWeight=0.36, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byref
ld a0, 0xD1FFAB1E(a0)
;; size=4 bbWeight=0.36 PerfScore 0.73
@@ -78,7 +75,7 @@ RWD00 dd	G_M20649_IG05 - G_M20649_IG02
dd	G_M20649_IG06 - G_M20649_IG02
-; Total bytes of code 140, prolog size 16, PerfScore 38.45, instruction count 30, allocated bytes for code 140 (MethodHash=a2b0af56) for method Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.CompilationUnitSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)+; Total bytes of code 128, prolog size 16, PerfScore 33.45, instruction count 30, allocated bytes for code 128 (MethodHash=a2b0af56) for method Microsoft.CodeAnalysis.CSharp.Syntax.InternalSyntax.CompilationUnitSyntax:GetSlot(int):Microsoft.CodeAnalysis.GreenNode:this (Tier1)
; ============================================================
Unwind Info:
@@ -89,7 +86,7 @@ Unwind Info:
E bit : 0
X bit : 0
Vers : 0
- Function Length : 35 (0x00023) Actual length = 140 (0x00008c)+ Function Length : 32 (0x00020) Actual length = 128 (0x000080)
---- Epilog scopes ----
---- Scope 0
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

+0 (0.00%) : 12080.dasm - IDEAEncryption:de_key_idea(char[],char[]) (Instrumented Tier0)

@@ -778,8 +778,8 @@ G_M48916_IG08: ; bbWeight=1, extend
;; size=32 bbWeight=1 PerfScore 20.00
G_M48916_IG09: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
; byrRegs -[a0]
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32

+0 (0.00%) : 12048.dasm - AssignJagged:Run():double:this (Tier1)

@@ -322,8 +322,8 @@ G_M27632_IG17: ; bbWeight=15.53, gcVars=0000200001000000 {V00 V01}, gcref
bnez t6, G_M27632_IG40
;; size=84 bbWeight=15.53 PerfScore 450.49
G_M27632_IG18: ; bbWeight=15.53, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
mulh a0, a0, s3
srli a1, a0, 63
srai a0, a0, 7

+0 (0.00%) : 12032.dasm - AssignJagged:second_assignments(int[][],short[][]) (Instrumented Tier0)

@@ -132,8 +132,8 @@ G_M6376_IG06: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
j G_M6376_IG08
;; size=24 bbWeight=1 PerfScore 12.00
G_M6376_IG07: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -230,8 +230,8 @@ G_M6376_IG12: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
j G_M6376_IG17
;; size=124 bbWeight=1 PerfScore 49.00
G_M6376_IG13: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -296,8 +296,8 @@ G_M6376_IG17: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
;; size=84 bbWeight=1 PerfScore 33.00
G_M6376_IG18: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
; byrRegs -[a0]
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -424,8 +424,8 @@ G_M6376_IG26: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
;; size=132 bbWeight=1 PerfScore 54.00
G_M6376_IG27: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
; byrRegs -[a0]
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -475,8 +475,8 @@ G_M6376_IG31: ; bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byre
; gcr arg pop 0
;; size=40 bbWeight=0.50 PerfScore 6.00
G_M6376_IG32: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -600,8 +600,8 @@ G_M6376_IG37: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
sw a0, -52(fp)
;; size=192 bbWeight=1 PerfScore 80.50
G_M6376_IG38: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -651,8 +651,8 @@ G_M6376_IG42: ; bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byre
; gcr arg pop 0
;; size=40 bbWeight=0.50 PerfScore 6.00
G_M6376_IG43: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -711,8 +711,8 @@ G_M6376_IG47: ; bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byre
j G_M6376_IG22
;; size=44 bbWeight=0.50 PerfScore 6.75
G_M6376_IG48: ; bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -813,8 +813,8 @@ G_M6376_IG50: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
sw a0, -44(fp)
;; size=204 bbWeight=1 PerfScore 86.50
G_M6376_IG51: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -864,8 +864,8 @@ G_M6376_IG55: ; bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byre
; gcr arg pop 0
;; size=40 bbWeight=0.50 PerfScore 6.00
G_M6376_IG56: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -949,8 +949,8 @@ G_M6376_IG62: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
sext.w t6, a0
addi ra, zero, 0xD1FFAB1E
beq t6, ra, G_M6376_IG63
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -1029,8 +1029,8 @@ G_M6376_IG66: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
blt t6, ra, G_M6376_IG62
;; size=16 bbWeight=1 PerfScore 6.50
G_M6376_IG67: ; bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -1113,8 +1113,8 @@ G_M6376_IG73: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
sext.w t6, a0
addi ra, zero, 0xD1FFAB1E
bne t6, ra, G_M6376_IG74
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -1193,8 +1193,8 @@ G_M6376_IG77: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
blt t6, ra, G_M6376_IG73
;; size=16 bbWeight=1 PerfScore 6.50
G_M6376_IG78: ; bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32
@@ -1242,8 +1242,8 @@ G_M6376_IG82: ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
sext.w t6, a0
addi ra, zero, 0xD1FFAB1E
blt t6, ra, G_M6376_IG72
- auipc t6, 0xD1FFAB1E- ld a0, 0xD1FFAB1E(t6)+ auipc a0, 0xD1FFAB1E+ ld a0, 0xD1FFAB1E(a0)
lui a1, 0xD1FFAB1E
addiw a1, a1, 0xD1FFAB1E
slli a1, a1, 32

Details

Size improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same size	Improvements (bytes)	Regressions (bytes)
test.mch	1,873	626	0	1,247	-9,576	+0

PerfScore improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same PerfScore	Improvements (PerfScore)	Regressions (PerfScore)	PerfScore Overall in FullOpts
test.mch	1,873	582	0	1,291	-1.58%	0.00%	-0.1680%

Context information

Collection	Diffed contexts	MinOpts	FullOpts	Missed, base	Missed, diff
test.mch	12,289	10,113	2,176	0 (0.00%)	0 (0.00%)

jit-analyze output

am11 · 2025-06-18T12:13:16Z

Either way, code sizes >2 Gb aren't likely, assuming them as default complicates the output asm.

What would it take to synthetically reproduce a scenario like that?

tomeksowi · 2025-06-18T12:28:03Z

What would it take to synthetically reproduce a scenario like that?

Just an artificially large test, I guess. The more interesting question is whether supporting >2Gb code has any added value to the end user (if such test wasn't developed yet, I would guess not).

jkotas · 2025-06-18T12:40:36Z

Sizes throughout the code manager and the JIT are limited to 32-bit. For example:

runtime/src/coreclr/inc/corjit.h

Lines 82 to 86 in f1a4b89

// Input arguments
uint32_t hotCodeSize; 
uint32_t coldCodeSize; 
uint32_t roDataSize; 
uint32_t xcptnsCount; 

. We are not interested in fixing this limitation. We just want to make sure that there are no silent integer overflows.

jkotas · 2025-06-18T13:07:00Z

For example,

runtime/src/coreclr/jit/emit.cpp

Lines 4474 to 4479 in 5951ad2

for (ig = emitIGlist, offs = 0; ig; ig = ig->igNext) 
 { 
 ig->igOffs = offs; 
assert(IsCodeAligned(ig->igOffs)); 
 offs += ig->igSize; 
 } 

looks suspect. It is not clear what prevents silent integer oveflows in this method.

risc-vv · 2025-06-24T14:30:55Z

RISC-V Release-CLR-VF2: 9087 / 9117 (99.67%)

=======================
passed: 9087
failed: 2
skipped: 600
killed: 28
------------------------
TOTAL tests: 9717
VIRTUAL time: 10h 42min 0s 831ms
REAL time: 43min 25s 774ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-QEMU: 9086 / 9116 (99.67%)

=======================
passed: 9086
failed: 2
skipped: 600
killed: 28
------------------------
TOTAL tests: 9716
VIRTUAL time: 35h 24min 33s 764ms
REAL time: 36min 12s 6ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-QEMU: 260854 / 261940 (99.59%)

=======================
passed: 260854
failed: 1080
skipped: 39
killed: 6
------------------------
TOTAL tests: 261979
VIRTUAL time: 30h 50min 16s 244ms
REAL time: 1h 11min 39s 765ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-VF2: 501232 / 502972 (99.65%)

=======================
passed: 501232
failed: 1731
skipped: 39
killed: 9
------------------------
TOTAL tests: 503011
VIRTUAL time: 21h 26min 53s 842ms
REAL time: 2h 18min 12s 658ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: b6cb65349e98c18102876c5fbb24af5bed5a3869
CI: 01a69d638efe9b8b18c2888449be98b4a6cde211
REPO: dotnet/runtime
BRANCH: main
CONFIG: Release
LIB_CONFIG: Release

tomeksowi · 2025-06-25T12:19:05Z

I'll be working on similar opportunities for e.g. INS_OPTS_C.

For now, it's a good enough savepoint to review. cc @dotnet/jit-contrib @jakobbotsch

tomeksowi added 6 commits June 18, 2025 09:04

Emit auipc+addi for non-reloc label addresses
5003398

Emit auipc+jalr for INS_OPT_JALR
58ea0cc

Fix jal target register
a4878f4

Fold branches for forward and backward jumps
33f52a6

Emit auipc+load/addi for cold sections INS_OPTS_RC
5aa7a52

cleanup
fc376f2

github-actionsBot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 18, 2025

dotnet-policy-serviceBot added the community-contribution Indicates that the PR has been added by a community member label Jun 18, 2025

am11 added arch-riscv Related to the RISC-V architecture labels Jun 18, 2025

This was referenced Jun 18, 2025
Test failure: Microsoft.Extensions.Configuration.EnvironmentVariables.Test.EnvironmentVariablesTest.BindingDoesNotThrowIfReloadedDuringBinding #109904
Closed
browser-wasm Windows build error #116746
Closed

clamp03 assigned tomeksowi Jun 23, 2025

overflow check
b6cb653

tomeksowi marked this pull request as ready for review June 24, 2025 13:37

tomeksowi changed the title ~~[RISC-V] Use auipc for all code addresses~~[RISC-V] Use auipc for code addresses in INS_OPTS_{RL,RC,JALR}Jun 25, 2025

tomeksowi mentioned this pull request Jul 1, 2025
[RISC-V] Use auipc for code addresses in INS_OPTS_C #117196
Merged

clamp03 requested a review from jakobbotsch July 10, 2025 01:51

jakobbotsch approved these changes Jul 10, 2025
View reviewed changes

jakobbotsch merged commit 45e14ea into dotnet:mainJul 10, 2025

github-actionsBot locked and limited conversation to collaborators Aug 10, 2025

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[RISC-V] Use auipc for code addresses in INS_OPTS_{RL,RC,JALR} - #116780

[RISC-V] Use auipc for code addresses in INS_OPTS_{RL,RC,JALR}#116780
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