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Less optimistic checking for const vector to pattern checks - #124599
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Fixesdotnet#124511 When checking a element of TBase size, ensure that no other bits other than the first bit are set
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
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Pull request overview
This PR fixes a JIT bug in ARM64 SVE intrinsics where constant vector patterns were incorrectly validated, leading to wrong results. The issue was that EvaluateSimdMaskToPattern only checked the lowest bit of each mask element, allowing invalid masks with extra bits set to pass validation.
Changes:
- Enhanced mask validation to check all bits in each TBase-sized element, not just the lowest bit
- Renamed
finalOnetofirstZerofor clarity - Updated comments to better explain the mask format and validation logic
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jakobbotsch
commented
Feb 20, 2026
Seems like one of the existing SVE regression tests is failing with this change. |
a74nh
commented
Feb 23, 2026
That's fixed now - just an issue with creating the mask for longs. |
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…net#124599) When checking a element of TBase size, ensure that no other bits other than the first bit are set
Fixes#124511
When checking a element of TBase size, ensure that no other bits other than the first bit are set