JIT: Accelerate floating->long casts on x86

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.

[saucecontrol]

This adds floating->long/ulong cast codegen for AVX-512 and AVX10.2 on x86. With this, all non-overflow casts are now hardware accelerated. This is the last bit pulled from #116805.

Typical Diff (double->long AVX-512):

- sub esp, 8- vzeroupper - vmovsd xmm0, qword ptr [esp+0x0C]- sub esp, 8- ; npt arg push 0- ; npt arg push 1- vmovsd qword ptr [esp], xmm0- call CORINFO_HELP_DBL2LNG- ; gcr arg pop 2+ vmovsd xmm0, qword ptr [esp+0x04]+ vcmpordsd k1, xmm0, xmm0+ vcmpge_oqsd k2, xmm0, qword ptr [@RWD00]+ vcvttpd2qq xmm0 {k1}{z}, xmm0+ vpblendmq xmm0 {k2}, xmm0, qword ptr [@RWD08] {1to2}+ vmovd eax, xmm0+ vpextrd edx, xmm0, 1- add esp, 8
ret 8
+RWD00 dq	43E0000000000000h+RWD08 dq	7FFFFFFFFFFFFFFFh-; Total bytes of code 31+; Total bytes of code 53

Full Diffs

Breakdown of the double->long asm:

; load the scalar doublevmovsd xmm0, qword ptr [esp+0x04]; set the low bit of k1 if the scalar value is not NaNvcmpordsd k1,xmm0,xmm0; set the low bit of k2 if the input was greater than or equal to 2^63 (nearest double greater than long.MaxValue)vcmpge_oqsd k2,xmm0, qword ptr [@RWD00]; convert, using k1 mask bit. if the mask bit is not set (meaning we have a NaN), set the value to zerovcvttpd2qqxmm0 {k1}{z},xmm0; if the low bit of k2 is set (meaning overflow), set the value to long.MaxValue, otherwise take the conversion resultvpblendmqxmm0 {k2},xmm0, qword ptr [@RWD08] {1to2}; extract the two 32-bit halves of the long resultvmovd eax,xmm0vpextrd edx,xmm0,1

[Copilot]

Pull request overview

This PR extends x86 JIT codegen to hardware-accelerate non-overflow floating→long/ulong casts using AVX-512 and AVX10.2, completing the remaining cast-acceleration work pulled from #116805.

Changes:

• Teach cast helper selection to allow floating↔long casts to stay intrinsic-based on x86 when AVX-512 is available.
• Add/extend x86 long decomposition logic to generate AVX-512/AVX10.2 sequences for floating→long/ulong and long→floating casts.
• Introduce a new AVX-512 scalar compare-mask intrinsic and wire it up for immediate bounds + containment.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerxarch.cpp	Refactors vector constant construction and adds containment support for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds immediate upper-bound handling for the new AVX-512 scalar compare-mask intrinsic.
src/coreclr/jit/hwintrinsiclistxarch.h	Introduces AVX512.CompareScalarMask as a new intrinsic mapping to vcmpss/vcmpsd with IMM.
src/coreclr/jit/flowgraph.cpp	Updates helper-requirement logic so x86 floating↔long casts can avoid helper calls when AVX-512 is available.
src/coreclr/jit/decomposelongs.cpp	Implements the AVX-512/AVX10.2-based lowering/decomposition sequences for floating↔long/ulong on x86.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[saucecontrol]

@dotnet/jit-contrib this is ready for review

diffs

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

[JulieLeeMSFT]

@EgorBo, please review this community PR.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

src/coreclr/jit/flowgraph.cpp:1347

• fgCastRequiresHelper on x86 currently only exempts long<->floating casts when InstructionSet_AVX512 is enabled. This PR adds long/floating cast acceleration that can use AVX10.2 (InstructionSet_AVX10v2) as well (e.g., DecomposeLongs::DecomposeCast checks compOpportunisticallyDependsOn(InstructionSet_AVX10v2)). If AVX10v2 is enabled while AVX512 is disabled/unavailable, morphing may still force a helper call and bypass the new codegen. Consider updating the x86 condition to treat AVX10v2 as sufficient (e.g., require helper only when neither AVX512 nor AVX10v2 is available).

#if defined(TARGET_X86) || defined(TARGET_ARM)
if ((varTypeIsLong(fromType) && varTypeIsFloating(toType)) ||
(varTypeIsFloating(fromType) && varTypeIsLong(toType)))
{
#if defined(TARGET_X86)
return !compOpportunisticallyDependsOn(InstructionSet_AVX512);
#else

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 1 comment.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated no new comments.

[tannergooding]

CC. @dotnet/jit-contrib, @EgorBo, @kg for secondary review on the community PR

[saucecontrol]

Pushed a change to simplify the IR. No change to the codegen.