Add AvxVnni.V512 hardware intrinsics by jamesburton · Pull Request #128365 · dotnet/runtime

jamesburton · 2026-05-19T12:39:19Z

Summary - Add the managed `AvxVnni.V512` surface for AVX-512 VNNI VPDPBUSD/VPDPWSSD intrinsics. - Wire CPUID AVX512-VNNI detection into the runtime/JIT `AVXVNNI_V512` instruction-set flag. - Extend VPDP codegen and LSRA handling to cover the new V512 intrinsic IDs. Closes#86849 ## Validation - `./build.cmd clr+libs -c Release -arch x64` - `./build.cmd clr -c Release -arch x64` - Strix Halo hardware probe: - `AvxVnni.V512.IsSupported == True` - `VPDPBUSD-zmm : got=160 want=160 OK` - `VPDPWSSD-zmm : got=8 want=8 OK` - `VPDPBUSDS-zmm: got=2147483647 ... OK` - JIT disassembly includes EVEX-512 forms: - `vpdpbusd zmm0, zmm1, ...` - `vpdpwssd zmm0, zmm1, ...` - `vpdpbusds zmm0, zmm1, ...`

Compatibility note

Existing R2R images that record Avx512Vnni now map to the more precise AVXVNNI_V512 JIT ISA instead of the broader AVX512v3 bucket. This is intentional: AVX512-VNNI is a distinct CPUID feature and the new managed API requires that specific capability, while retaining the existing R2R numeric value (Avx512Vnni = 79).

Copilot

Pull request overview

Note

Copilot was unable to run its full agentic suite in this review.

Adds AVX-VNNI 512-bit (AVX512-VNNI) hardware intrinsics support exposed as the new AvxVnni.V512 nested class, wiring it through the JIT, runtime, CPU feature detection, R2R metadata, and adding a sample test project.

Changes:

New AvxVnni.V512 nested class with MultiplyWideningAndAdd/MultiplyWideningAndAddSaturate overloads (byte/sbyte and short/short) on Vector512<int>.
New AVXVNNI_V512 instruction set plumbed through CorInfo/JIT/R2R/cpufeatures, with AVX512 as its implication and AVXVNNI as its parent ISA.
New test project (AvxVnni_V512) plus a handwritten sample test that exercises VPDPBUSD/VPDPBUSDS/VPDPWSSD on 512-bit vectors.

Reviewed changes

Copilot reviewed 25 out of 25 changed files in this pull request and generated 6 comments.

Show a summary per file

File	Description
src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/X86/AvxVnni.cs	Adds `AvxVnni.V512` nested class with the 4 VNNI 512-bit intrinsics.
src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/X86/AvxVnni.PlatformNotSupported.cs	PNSE stubs for new V512 APIs.
src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs	Reference assembly entries for the new V512 APIs.
src/native/minipal/cpufeatures.h	Adds `XArchIntrinsicConstants_Avx512Vnni` bit.
src/native/minipal/cpufeatures.c	Detects AVX512-VNNI via CPUID leaf 7 ECX bit 11.
src/coreclr/inc/corinfoinstructionset.h	Inserts new `AVXVNNI_V512` enum value (shifts subsequent values), implication and PNSE mapping for R2R.
src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs	Mirrors the new enum value and its forward/reverse implications.
src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt	Defines `AVXVNNI_V512` instruction set and AVX512 implication.
src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs	Adds `Avx512Vnni` flag bit and mapping from instruction set.
src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs	Maps new ISA to existing `Avx512Vnni` R2R set.
src/coreclr/tools/Common/InstructionSetHelpers.cs	Adds `avxvnni_v512` to optimistic set on Intel.
src/coreclr/jit/hwintrinsiclistxarch.h	Defines NI list entries for the new V512 intrinsics.
src/coreclr/jit/hwintrinsicxarch.cpp	Adds AVXVNNI→AVXVNNI_V512 mapping for V512 versioning.
src/coreclr/jit/hwintrinsiccodegenxarch.cpp	Includes new NIs in the special codegen path.
src/coreclr/jit/hwintrinsic.cpp	Adds ISA range entry for AVXVNNI_V512.
src/coreclr/jit/lsraxarch.cpp	Adds LSRA handling for new NIs.
src/coreclr/jit/compiler.cpp	Enables `AVXVNNI_V512` when `EnableAVX512v3` config is set.
src/coreclr/vm/codeman.cpp	Sets the JIT compile flag based on CPU detection.
src/coreclr/inc/jiteeversionguid.h	Bumps JIT/EE GUID.
src/tests/JIT/HardwareIntrinsics/X86_Avx/AvxVnni_V512/*	New test project + handwritten sample test.

jamesburton · 2026-05-19T12:45:44Z

@dotnet-policy-service agree

jamesburton · 2026-05-19T12:47:17Z

@copilot apply changes based on the comments in this thread

Copilot

Pull request overview

Copilot reviewed 25 out of 25 changed files in this pull request and generated 6 comments.

Copilot

Pull request overview

Copilot reviewed 25 out of 25 changed files in this pull request and generated 4 comments.

tannergooding · 2026-05-19T14:46:50Z

-- Could you resolve any copilot comments that have already been addressed to help make it easier to review and know what is or isn't pending?

Copilot

Pull request overview

Copilot reviewed 27 out of 27 changed files in this pull request and generated 3 comments.

jamesburtonfnz · 2026-05-19T14:55:56Z

Sure ... I'm actively looping through the feedback and will update each as they are resolved ... I see it is quite zealous and the stream of updates keeps a constant rebasing challenge but hopefully should be able to tidy this up enough today. I have identified 4 more related issues that I hope to apply that are related to this to unlock even further performance with some of these newer operators.

…

________________________________ From: Tanner Gooding ***@***.***> Sent: 19 May 2026 15:47 To: dotnet/runtime ***@***.***> Cc: James Burton ***@***.***>; Comment ***@***.***> Subject: Re: [dotnet/runtime] Add AvxVnni.V512 hardware intrinsics (PR #128365) [https://avatars.githubusercontent.com/u/10487869?s=20&v=4]tannergooding left a comment (dotnet/runtime#128365)<#128365 (comment)>

-- Could you resolve any copilot comments that have already been addressed to help make it easier to review and know what is or isn't pending? — Reply to this email directly, view it on GitHub<#128365 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/BIV6FFYGY6EGX5KSJF5UDND43RXXHAVCNFSM6AAAAACZEJ6OKCVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHM2DIOBYHE2DCMBQGU>. Triage notifications on the go with GitHub Mobile for iOS<https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675> or Android<https://play.google.com/store/apps/details?id=com.github.android&referrer=utm_campaign%3Dnotification-email%26utm_medium%3Demail%26utm_source%3Dgithub>. You are receiving this because you commented.Message ID: ***@***.***>

Copilot

Pull request overview

Copilot reviewed 27 out of 27 changed files in this pull request and generated 5 comments.

Copilot

Pull request overview

Copilot reviewed 27 out of 27 changed files in this pull request and generated 4 comments.

Copilot

Pull request overview

Copilot reviewed 27 out of 27 changed files in this pull request and generated 5 comments.

The V512VersionOfIsa wire-up correctly routes AvxVnni.V512 lookups through AVX512v3 (via lookupIsa), and binarySearchId(AVX512v3, "MultiplyWideningAndAdd") resolves to NI_AVX512v3_MultiplyWideningAndAdd (the dedicated EVEX-encoded V512 entry that already had its codegen and LSRA cases). Pre-fix, that lookup path was unreachable because V512VersionOfIsa returned NONE for the AVXVNNI / AVX512v3 enclosing. The default branch in Lowering::ContainCheckHWIntrinsic's 3-operand SimpleSIMD path asserted that the intrinsicId was DivRem or in the FIRST_NI_AVXVNNI..LAST_NI_AVXVNNIINT_V512 range. NI_AVX512v3_M* intrinsics are declared earlier in hwintrinsiclistxarch.h (around line 1075), so their NI values fall below FIRST_NI_AVXVNNI and the range check fails. ILC SIGABRTs (exit 134) on the X64Avx512 / X64Avx512_VectorT512 NativeAOT smoke tests which now exercise AvxVnni.V512.MultiplyWideningAndAdd as a real intrinsic. Add the two NI_AVX512v3 multiply-widening NIs to the assert. Behavior is unchanged (TryMakeSrcContainedOrRegOptional is the right containment pattern — same as the VNNI variants). AvxVnni.V512.IsSupported still verified True on Zen5 with VPDPBUSD512 lane0 = 24. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

jamesburton · 2026-06-15T23:08:50Z

Pushed 80cb14ce181.

Root cause of the persistent NativeAOT Debug failures (exit 134 SIGABRT in ILC during X64Avx512 / X64Avx512_VectorT512 smoke tests): the V512VersionOfIsa fix correctly enabled the AVX512v3 lookup path, which resolves AvxVnni.V512.MultiplyWideningAndAdd to NI_AVX512v3_MultiplyWideningAndAdd (the dedicated EVEX entry at hwintrinsiclistxarch.h:1075-1076). Pre-fix that path was unreachable, so the test compiled the call as a regular method (the recursive [Intrinsic] stub) and ILC never reached the actual lowering path.

Now that the lookup resolves, lowering's default 3-operand SimpleSIMD branch asserted the intrinsicId was DivRem or in FIRST_NI_AVXVNNI..LAST_NI_AVXVNNIINT_V512. NI_AVX512v3_M* is declared earlier in the table so its NI value falls below the range — assert fires, ILC SIGABRTs.

LSRA (lsraxarch.cpp:2751-2752) and codegen (hwintrinsiccodegenxarch.cpp:905-906) already had explicit cases for NI_AVX512v3_MultiplyWideningAndAdd* — just the lowering assert was missing them. Added the two NIs to the assert, no behavior change (TryMakeSrcContainedOrRegOptional is the right containment pattern).

AvxVnni.V512.IsSupported = True + VPDPBUSD512 lane0 = 24 still verified on Zen5.

jamesburton · 2026-06-19T11:17:05Z

@dhartglassMSFT — gentle nudge as Tanner CC'd you for secondary review. Head 80cb14ce181 has been stable since 2026-06-15; no further changes pending.

Quick orientation if helpful:

Net change since Tanner's approval: 1 merge-from-main (JIT-EE GUID bump only) + 3 small follow-ups addressing his V512VersionOfIsa / NativeAOT feedback.
CI: Windows NativeAOT Debug/Checked/Release all green — confirms the lowerxarch.cpp:10250 assert extension is doing its job.
52 Linux failures are all the same Docker-registry auth flake (mcr.microsoft.com … no basic auth credentials pulling prereq containers) — pure Helix-infra cascade, not code.

Happy to walk through any of the follow-up commits if useful. Thanks!

# Conflicts: # src/coreclr/inc/jiteeversionguid.h

jamesburton · 2026-06-22T15:56:25Z

CI status update on head 098843d73a1 (post-merge): 4 remaining red checks, none related to this PR.

Check	Verdict
`Libraries Test Run checked coreclr linux_musl x64 Debug`	Helix-infra flake — `Unable to pull image mcr.microsoft.com/dotnet-buildtools/prereqs:alpine-3.23-helix-amd64@sha256:…` exit `-4` on 3 work items. Same Docker-registry pull pattern as the earlier 52-failure cascade, just a different prereq image.
`Libraries Test Run checked coreclr osx arm64 Debug`	Known flake — `Microsoft.Extensions.FileProviders.PhysicalFileProviderTests.TokensFiredForNewDirectoryContentsOnRename` matched against #104823 (PhysicalFilesWatcher symlink). Libraries-side test, no JIT/intrinsics correlation.
`runtime`	Rollup of the two legs above.
`Build Analysis`	Gates on the rollup.

The build's PR-file correlation against the failing tests is zero (Microsoft.Extensions.FileProviders.Physical/tests/PhysicalFileProviderTests.cs and the alpine-3.23 docker pull aren't in our diff). Happy to retry the legs on request, but nothing here to fix in code.

# Conflicts: # src/coreclr/inc/jiteeversionguid.h

jamesburton · 2026-06-26T20:29:52Z

Refreshed against upstream/main again (head 9a72325abfa, JIT-EE GUID rotated for the merge). The intrinsic surface and the V512VersionOfIsa + lowering-assert fixes are unchanged from before; rebuild + AvxVnni.V512 functional probe on Zen5 still confirm VPDPBUSD512 lane0 = 24 FUNCTIONAL_OK=True.

This is the third merge-from-main cycle since Tanner's original approval, and each one invalidates the review and re-runs CI. Could we land the secondary review (or re-approval) when convenient? Happy to address any remaining concerns inline — the longer the gap, the more cycles like this we accumulate, and there are downstream consumers (BF16 kernel work on Zen5) waiting on this to merge before they can drop their workarounds. No urgency to disturb your weekend — flagging for when the queue clears next week.

tannergooding · 2026-06-26T22:09:09Z

CC. @dotnet/jit-contrib this is still pending secondary review.

tannergooding · 2026-06-27T18:51:45Z

/ba-g all jobs finished, build analysis stuck

jamesburton · 2026-06-28T15:48:38Z

Thanks @tannergooding, @EgorBo, @dhartglassMSFT — appreciate the review attention and the patience through the merge-rebase cycles. Downstream consumers (BF16 quant kernels on Zen5 / Strix Halo) can finally drop their workarounds once this is in the next nightly. 🙏

## Summary - Add the managed `AvxVnni.V512` surface for AVX-512 VNNI VPDPBUSD/VPDPWSSD intrinsics. - Wire CPUID AVX512-VNNI detection into the runtime/JIT `AVXVNNI_V512` instruction-set flag. - Extend VPDP codegen and LSRA handling to cover the new V512 intrinsic IDs. Closes#86849 ## Validation - `./build.cmd clr+libs -c Release -arch x64` - `./build.cmd clr -c Release -arch x64` - Strix Halo hardware probe: - `AvxVnni.V512.IsSupported == True` - `VPDPBUSD-zmm : got=160 want=160 OK` - `VPDPWSSD-zmm : got=8 want=8 OK` - `VPDPBUSDS-zmm: got=2147483647 ... OK` - JIT disassembly includes EVEX-512 forms: - `vpdpbusd zmm0, zmm1, ...` - `vpdpwssd zmm0, zmm1, ...` - `vpdpbusds zmm0, zmm1, ...` ## Compatibility note Existing R2R images that record `Avx512Vnni` now map to the more precise `AVXVNNI_V512` JIT ISA instead of the broader `AVX512v3` bucket. This is intentional: AVX512-VNNI is a distinct CPUID feature and the new managed API requires that specific capability, while retaining the existing R2R numeric value (`Avx512Vnni = 79`). --------- Co-authored-by: Your Name <you@example.com> Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

jamesburton requested a review from MichalStrehovsky as a code owner May 19, 2026 12:39

CopilotAI review requested due to automatic review settings May 19, 2026 12:39

github-actionsBot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 19, 2026

dotnet-policy-serviceBot added the community-contribution Indicates that the PR has been added by a community member label May 19, 2026