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Remove CORINFO_HELP_ASSIGN_BYREF - #128542
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Pull request overview
This PR removes the CORINFO_HELP_ASSIGN_BYREF / JIT_ByRefWriteBarrier helper from the JIT/EE boundary and ReadyToRun format, and replaces the JIT’s “cpobj with interleaved GC pointers” lowering/codegen path with either (a) decomposition into per-slot ASSIGN_REF write barriers (for small GC pointer counts) or (b) the existing bulk write-barrier helper (CORINFO_HELP_BULK_WRITEBARRIER). It also bumps the ReadyToRun major version to reflect the serialized format change.
Changes:
- Delete the
ASSIGN_BYREFhelper surface area (helper IDs, write-barrier stubs/AV markers, and per-arch asm implementations) across VM, runtime, NativeAOT EH helper marking, and AOT tooling. - Remove the
CpObj*block op kinds and all backendgenCodeForCpObjimplementations; introduceTryDecomposeBlockStoreAsIndirs+LowerBlockStoreAsGcBulkCopyCallas the new lowering strategy for GC-containing struct copies. - Bump ReadyToRun major version to 19 and reserve helper ID
0x32(formerlyByRefWriteBarrier) to avoid reuse.
Reviewed changes
Copilot reviewed 70 out of 70 changed files in this pull request and generated 1 comment.
Show a summary per file
| File | Description |
|---|---|
| src/coreclr/vm/wasm/helpers.cpp | Removes wasm helper end marker and AV location globals for byref write barrier. |
| src/coreclr/vm/threads.cpp | Stops registering CORINFO_HELP_ASSIGN_BYREF helper in InitThreadManager; updates AMD64 comment. |
| src/coreclr/vm/riscv64/asmhelpers.S | Removes JIT_ByRefWriteBarrier implementation; adjusts comments about incremented regs. |
| src/coreclr/vm/loongarch64/asmhelpers.S | Removes JIT_ByRefWriteBarrier implementation; adjusts comments about incremented regs. |
| src/coreclr/vm/jitinterface.h | Removes RhpByRefAssignRef* declarations/mapping and JIT_ByRefWriteBarrier decl. |
| src/coreclr/vm/i386/jithelp.S | Deletes x86 JIT_ByRefWriteBarrier helper macro/entry and its inclusion in the group. |
| src/coreclr/vm/i386/jithelp.asm | Deletes x86 JIT_ByRefWriteBarrier helper macro/entry and its inclusion in the group. |
| src/coreclr/vm/excep.cpp | Removes byref write barrier end marker, AV locations, and helper-range checks. |
| src/coreclr/vm/arm64/patchedcode.S | Removes ARM64 JIT_ByRefWriteBarrier; updates comments for remaining helpers/return stubs. |
| src/coreclr/vm/arm64/patchedcode.asm | Removes ARM64 JIT_ByRefWriteBarrier; updates comments for remaining helpers/return stubs. |
| src/coreclr/vm/arm/stubs.cpp | Removes ARM byref barrier variants from stub declarations/mapping/validation. |
| src/coreclr/vm/arm/patchedcode.S | Removes ARM JIT_ByRefWriteBarrier region from patched code blob. |
| src/coreclr/vm/arm/asmhelpers.S | Removes ARM byref write barrier helper macro and descriptor entries. |
| src/coreclr/vm/amd64/jithelpers_fast.S | Removes AMD64 Unix JIT_ByRefWriteBarrier implementation. |
| src/coreclr/vm/amd64/JitHelpers_Fast.asm | Removes AMD64 Windows JIT_ByRefWriteBarrier implementation. |
| src/coreclr/tools/Common/JitInterface/CorInfoHelpFunc.cs | Removes CORINFO_HELP_ASSIGN_BYREF from managed mirror enum. |
| src/coreclr/tools/Common/Internal/Runtime/ReadyToRunConstants.cs | Reserves 0x32 with a “do not reuse” comment in tool-side helper enum. |
| src/coreclr/tools/aot/ILCompiler.RyuJit/JitInterface/CorInfoImpl.RyuJit.cs | Drops mapping from ASSIGN_BYREF to ByRefWriteBarrier R2R helper. |
| src/coreclr/tools/aot/ILCompiler.Reflection.ReadyToRun/ReadyToRunSignature.cs | Removes signature pretty-printing for ByRefWriteBarrier. |
| src/coreclr/tools/aot/ILCompiler.ReadyToRun/JitInterface/CorInfoImpl.ReadyToRun.cs | Drops mapping from ASSIGN_BYREF to ByRefWriteBarrier R2R helper. |
| src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/JitHelper.cs | Removes ReadyToRunHelper.ByRefWriteBarrier entry point logic. |
| src/coreclr/runtime/riscv64/WriteBarriers.S | Removes RhpByRefAssignRef implementation/AV alternate entry. |
| src/coreclr/runtime/portable/WriteBarriers.cpp | Removes portable stub for RhpByRefAssignRef. |
| src/coreclr/runtime/loongarch64/WriteBarriers.S | Removes RhpByRefAssignRef; updates comment about incremented regs in remaining helper. |
| src/coreclr/runtime/i386/WriteBarriers.S | Removes RhpByRefAssignRef implementation and AV alternate entries. |
| src/coreclr/runtime/i386/WriteBarriers.asm | Removes RhpByRefAssignRef implementation and AV alternate entries. |
| src/coreclr/runtime/arm64/WriteBarriers.S | Removes RhpByRefAssignRefArm64 implementation/AV alternate entry. |
| src/coreclr/runtime/arm64/WriteBarriers.asm | Removes RhpByRefAssignRefArm64 implementation/AV alternate entry. |
| src/coreclr/runtime/arm/WriteBarriers.S | Removes RhpByRefAssignRef implementation and AV labels. |
| src/coreclr/runtime/amd64/WriteBarriers.S | Removes RhpByRefAssignRef implementation and AV alternate entries (incl. Apple unwind workaround). |
| src/coreclr/runtime/amd64/WriteBarriers.asm | Removes RhpByRefAssignRef implementation and AV alternate entries. |
| src/coreclr/nativeaot/Runtime/EHHelpers.cpp | Removes byref write barrier AV locations from NativeAOT helper-range detection. |
| src/coreclr/jit/utils.cpp | Removes CORINFO_HELP_ASSIGN_BYREF from helper call property initialization. |
| src/coreclr/jit/targetx86.h | Removes x86 ASSIGN_BYREF register/killset documentation and masks. |
| src/coreclr/jit/targetwasm.h | Removes wasm byref write barrier reg/killset defines. |
| src/coreclr/jit/targetriscv64.h | Removes RISCV64 byref write barrier reg/killset defines. |
| src/coreclr/jit/targetloongarch64.h | Removes LoongArch64 byref write barrier reg/killset defines. |
| src/coreclr/jit/targetarm64.h | Removes ARM64 byref write barrier reg/killset defines. |
| src/coreclr/jit/targetarm.h | Removes ARM byref write barrier reg/killset defines. |
| src/coreclr/jit/targetamd64.h | Removes AMD64 byref write barrier killset defines and related commentary. |
| src/coreclr/jit/lsraxarch.cpp | Removes CpObj-specific LSRA register assignment logic for xarch. |
| src/coreclr/jit/lsrariscv64.cpp | Removes CpObj-specific LSRA register assignment logic for riscv64. |
| src/coreclr/jit/lsraloongarch64.cpp | Removes CpObj-specific LSRA register assignment logic for loongarch64. |
| src/coreclr/jit/lsrabuild.cpp | Removes CpObj killset handling that depended on ASSIGN_BYREF. |
| src/coreclr/jit/lsraarmarch.cpp | Removes CpObj-specific LSRA register assignment logic for arm/arm64. |
| src/coreclr/jit/lowerxarch.cpp | Changes GC-containing struct copy lowering to decompose-or-bulk-helper; adjusts stack/off-heap handling. |
| src/coreclr/jit/lowerwasm.cpp | Uses decompose-or-bulk-helper for GC-containing struct copies on wasm. |
| src/coreclr/jit/lowerriscv64.cpp | Uses decompose-or-bulk-helper for GC-containing struct copies on riscv64. |
| src/coreclr/jit/lowerloongarch64.cpp | Uses decompose-or-bulk-helper for GC-containing struct copies on loongarch64. |
| src/coreclr/jit/lowerarmarch.cpp | Uses decompose-or-bulk-helper for GC-containing struct copies on arm/arm64. |
| src/coreclr/jit/lower.h | Replaces TryLowerBlockStoreAsGcBulkCopyCall with LowerBlockStoreAsGcBulkCopyCall and adds TryDecomposeBlockStoreAsIndirs. |
| src/coreclr/jit/lower.cpp | Implements decomposition into per-slot indirections and the bulk write-barrier fallback lowering. |
| src/coreclr/jit/gentree.h | Removes CpObj-specific BlkOpKind enum values. |
| src/coreclr/jit/gentree.cpp | Removes debug printing for CpObj BlkOpKind values. |
| src/coreclr/jit/emit.cpp | Removes special-case GC-reg-kill handling for ASSIGN_BYREF. |
| src/coreclr/jit/codegenxarch.cpp | Removes CpObj codegen path and related block-kind dispatch. |
| src/coreclr/jit/codegenwasm.cpp | Removes byref write barrier signature comment. |
| src/coreclr/jit/codegenriscv64.cpp | Removes CpObj codegen path and related block-kind dispatch. |
| src/coreclr/jit/codegenloongarch64.cpp | Removes CpObj codegen path and related block-kind dispatch. |
| src/coreclr/jit/codegencommon.cpp | Removes helper killset case for ASSIGN_BYREF. |
| src/coreclr/jit/codegenarmarch.cpp | Removes CpObj block-kind dispatch. |
| src/coreclr/jit/codegenarm64.cpp | Removes CpObj codegen path implementation. |
| src/coreclr/jit/codegenarm.cpp | Removes CpObj codegen path implementation. |
| src/coreclr/jit/codegen.h | Removes genCodeForCpObj declaration. |
| src/coreclr/inc/readytorunhelpers.h | Removes READYTORUN_HELPER_ByRefWriteBarrier mapping macro entry. |
| src/coreclr/inc/readytorun.h | Bumps R2R major/minimum major to 19; reserves helper slot 0x32; documents the format break. |
| src/coreclr/inc/jithelpers.h | Removes CORINFO_HELP_ASSIGN_BYREF helper entry. |
| src/coreclr/inc/jiteeversionguid.h | Updates JITEEVersionIdentifier to reflect the interface change. |
| src/coreclr/inc/corinfo.h | Removes CORINFO_HELP_ASSIGN_BYREF from CorInfoHelpFunc. |
| docs/design/coreclr/botr/readytorun-format.md | Updates R2R helper enum docs to reserve 0x32 and note removal. |
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MemberAuthor
@EgorBot -amd -arm usingBenchmarkDotNet.Attributes;usingBenchmarkDotNet.Running;BenchmarkSwitcher.FromAssembly(typeof(Benchmarks).Assembly).Run(args);publicclassBenchmarks{privateMyStructa1;privateMyStructa2;[Benchmark]publicvoidCopy(){a1=a2;}}recordstructMyStruct(longN1,longN2,longN3,longN4,longN5,stringA,stringB); |
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Pull request overview
Copilot reviewed 32 out of 32 changed files in this pull request and generated 1 comment.
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src/coreclr/jit/lower.cpp:10167
- LowerBlockStoreAsGcBulkCopyCall now unconditionally drops a GT_IND source without preserving/handling volatile semantics (previously this path explicitly refused volatile sources/stores). If
datais a volatile indirection (e.g. reading from a volatile struct field), removing the GT_IND loses the volatile flag, and the resulting CORINFO_HELP_BULK_WRITEBARRIER call is not wrapped with the usual memory barrier nodes (compare with LowerBlockStoreAsHelperCall). This risks incorrect volatile ordering/semantics on non-xarch targets. Consider either (1) keeping the earlier bail-out for volatile source/store and forcing decomposition in those cases, or (2) explicitly inserting the appropriate BARRIER_* nodes around the helper call and preserving volatile-source behavior.
// or layouts with too many GC pointers to decompose efficiently). Volatile
// semantics are preserved by the helper call itself — the call acts as a
// compiler memory barrier and the helper uses atomic per-slot stores.
//
// Arguments:
// blk - The block store node to lower
//
void Lowering::LowerBlockStoreAsGcBulkCopyCall(GenTreeBlk* blk)
{
assert(blk->OperIs(GT_STORE_BLK));
assert(!blk->OperIsInitBlkOp());
assert(blk->GetLayout()->HasGCPtr());
assert(!blk->IsAddressNotOnHeap(m_compiler));
GenTree* dest = blk->Addr();
GenTree* data = blk->Data();
if (data->OperIs(GT_IND))
{
// Drop GT_IND nodes
BlockRange().Remove(data);
data = data->AsIndir()->Addr();
}
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jakobbotsch
approved these changes
May 27, 2026
Co-authored-by: Jakob Botsch Nielsen <Jakob.botsch.nielsen@gmail.com>
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This was referenced May 28, 2026
EgorBo added a commit
that referenced
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May 29, 2026
Follow up #128542 Not sure if it's worth bumping the R2R format for this if nothing else needs it, but let's see if it compiles --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Co-authored-by: Jan Kotas <jkotas@microsoft.com>
This was referenced May 30, 2026
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EgorBo added a commit
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Jul 8, 2026
LowerCopyBlockStore/LowerInitBlockStore dropped write barriers for a stack destination containing GC pointers (correct) but then, for sizes above the unroll threshold, fell back to the managed CORINFO_HELP_MEMCPY (SpanHelpers.Memmove) / CORINFO_HELP_MEMZERO (SpanHelpers.ClearWithoutReferences) helpers. Those calls are GC-safe points, so a GC triggered mid-operation could observe torn GC pointers in the partially-written, GC-reported stack destination and corrupt the heap. Only take the "no write barriers" copy shortcut when the copy is actually unrolled into a single non-interruptible region; otherwise stay on the GC-aware CpObj path. Route zeroing of any GC-pointer struct (stack or heap) to the atomic pointer-sized zeroing loop instead of the helper. Copy regression introduced by dotnet#128542. Fixesdotnet#130286 Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
EgorBo added a commit
that referenced
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Jul 8, 2026
Fixes#130286. For a stack-target struct copy/zero containing GC pointers, `LowerCopyBlockStore`/`LowerInitBlockStore` correctly dropped write barriers but, above the unroll threshold, fell back to the managed `CORINFO_HELP_MEMCPY` (`Memmove`) / `CORINFO_HELP_MEMZERO` (`ClearWithoutReferences`) helpers. Those are GC-safe points, so a GC mid-operation could observe torn GC pointers in the partially-written, GC-reported stack destination and corrupt the heap. Fix: - Copy: only take the "no write barriers" shortcut when the copy is actually unrolled (single non-interruptible region); otherwise stay on the GC-aware CpObj path. - Zero: route zeroing of any GC-pointer struct (stack or heap) to the atomic pointer-sized loop instead of the helper. The copy regression was introduced by #128542. Verified: SPMI `replay -f benchmarks.run` clean; asmdiffs limited to large GC structs now using the GC-safe path; before/after codegen confirms `MEMCPY`→`BULK_WRITEBARRIER` and `MEMZERO`→zeroing loop. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
eiriktsarpalis pushed a commit
that referenced
this pull request
Jul 15, 2026
This PR removes `CORINFO_HELP_ASSIGN_BYREF` write-barrier (which is
basically `CORINFO_HELP_CHECKED_ASSIGN_REF` with a custom calling
convention), it is replaced by either `CORINFO_HELP_ASSIGN_REF` or
`CORINFO_HELP_CHECKED_ASSIGN_REF`. As a side effect we no longer use
slow `rep movsq` on x64 for gaps between GC slots and may use SIMD. The
motivation that `CORINFO_HELP_ASSIGN_BYREF` was very useful for large
struct copies, but we now have a bulk write barrier for those.
NOTE: A lot of code (>1000-2000 LOC) can be removed from CoreCLR/NAOT
side as dead as well since `CORINFO_HELP_ASSIGN_BYREF` is unused now,
but that's for another PR and might require R2R bump.
```cs
class MyClass
{
MyStruct _fld;
void SetA(MyStruct value) => _fld = value;
}
record struct MyStruct(long N1, long N2, long N3, long N4, long N5, string A, string B);
```
```diff
- push rdi
push rsi
+ push rbx
+ mov rbx, rdx
- lea rdi, bword ptr [rcx+0x08]
- mov rsi, rdx
- call CORINFO_HELP_ASSIGN_BYREF
- call CORINFO_HELP_ASSIGN_BYREF
- mov ecx, 5
- rep movsq
+ lea rsi, bword ptr [rcx+0x08]
+ mov rdx, gword ptr [rbx]
+ mov rcx, rsi
+ call CORINFO_HELP_ASSIGN_REF
+ mov rdx, gword ptr [rbx+0x08]
+ lea rcx, bword ptr [rsi+0x08]
+ call CORINFO_HELP_ASSIGN_REF
+ vmovdqu ymm0, ymmword ptr [rbx+0x10]
+ vmovdqu ymmword ptr [rsi+0x10], ymm0
+ mov rax, qword ptr [rbx+0x30]
+ mov qword ptr [rsi+0x30], rax
+ vzeroupper
+ pop rbx
pop rsi
- pop rdi
ret
```
## Benchmark
```cs
using BenchmarkDotNet.Attributes;
using BenchmarkDotNet.Running;
using System.Runtime.CompilerServices;
BenchmarkSwitcher.FromAssembly(typeof(Benchmarks).Assembly).Run(args);
public class Benchmarks
{
MyStruct src, dst;
[Benchmark]
public void Heap() => dst = src;
}
public struct MyStruct
{
public string A; public InlineArray4<long> G; public string B;
}
```
#### INTEL XEON PLATINUM 8573C | Method | Toolchain | Mean | Error | Ratio | |------- |----------------------- |----------:|----------:|------:|
| Heap | PR #128542 | 2.724 ns | 0.0628 ns | 1.00 | | Heap | main | 31.152 ns | 0.2597 ns | 11.44 |
#### AMD EPYC 9V45 2.60GHz
| Method | Toolchain | Mean | Error | Ratio | |------- |------------------- |----------:|----------:|------:|
| Heap | PR #128542 | 1.968 ns | 0.0603 ns | 1.00 | | Heap | main | 13.121 ns | 0.0067 ns | 6.68 |
#### Apple M4
| Method | Toolchain | Mean | Error | Ratio |
|------- |------------------- |----------:|----------:|------:|
| Heap | PR #128542 | 0.9574 ns | 0.0021 ns | 1.00 |
| Heap | main | 1.4646 ns | 0.0053 ns | 1.53 |
Sligtly less difference on arm64 where we don't have slow `movsq` for
nongc gaps.
---------
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Co-authored-by: Jakob Botsch Nielsen <Jakob.botsch.nielsen@gmail.com>eiriktsarpalis pushed a commit
that referenced
this pull request
Jul 15, 2026
Follow up #128542 Not sure if it's worth bumping the R2R format for this if nothing else needs it, but let's see if it compiles --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Co-authored-by: Jan Kotas <jkotas@microsoft.com>
eiriktsarpalis pushed a commit
that referenced
this pull request
Jul 15, 2026
Fixes#130286. For a stack-target struct copy/zero containing GC pointers, `LowerCopyBlockStore`/`LowerInitBlockStore` correctly dropped write barriers but, above the unroll threshold, fell back to the managed `CORINFO_HELP_MEMCPY` (`Memmove`) / `CORINFO_HELP_MEMZERO` (`ClearWithoutReferences`) helpers. Those are GC-safe points, so a GC mid-operation could observe torn GC pointers in the partially-written, GC-reported stack destination and corrupt the heap. Fix: - Copy: only take the "no write barriers" shortcut when the copy is actually unrolled (single non-interruptible region); otherwise stay on the GC-aware CpObj path. - Zero: route zeroing of any GC-pointer struct (stack or heap) to the atomic pointer-sized loop instead of the helper. The copy regression was introduced by #128542. Verified: SPMI `replay -f benchmarks.run` clean; asmdiffs limited to large GC structs now using the GC-safe path; before/after codegen confirms `MEMCPY`→`BULK_WRITEBARRIER` and `MEMZERO`→zeroing loop. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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This PR removes
CORINFO_HELP_ASSIGN_BYREFwrite-barrier (which is basicallyCORINFO_HELP_CHECKED_ASSIGN_REFwith a custom calling convention), it is replaced by eitherCORINFO_HELP_ASSIGN_REForCORINFO_HELP_CHECKED_ASSIGN_REF. As a side effect we no longer use slowrep movsqon x64 for gaps between GC slots and may use SIMD. The motivation thatCORINFO_HELP_ASSIGN_BYREFwas very useful for large struct copies, but we now have a bulk write barrier for those.NOTE: A lot of code (>1000-2000 LOC) can be removed from CoreCLR/NAOT side as dead as well since
CORINFO_HELP_ASSIGN_BYREFis unused now, but that's for another PR and might require R2R bump.Benchmark
INTEL XEON PLATINUM 8573C
AMD EPYC 9V45 2.60GHz
Apple M4
Sligtly less difference on arm64 where we don't have slow
movsqfor nongc gaps.