JIT, AOT preinit, and CoreLib: Saturate float/double conversions to small integral types

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;

src/coreclr/jit/assertionprop.cpp

@@ -409,6 +409,26 @@ static Range GetRange(Compiler* comp, GenTree* tree, BasicBlock* block, ASSERT_V
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::ByteMax};
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ {
+ return {SymbolicIntegerValue::ByteMin, SymbolicIntegerValue::ByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ {
+ return {SymbolicIntegerValue::ShortMin, SymbolicIntegerValue::ShortMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UByteMax};
+ }
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::UShortMax};
+ }
+
  case NI_System_Runtime_CompilerServices_RuntimeHelpers_IsKnownConstant:
  {
  return {SymbolicIntegerValue::Zero, SymbolicIntegerValue::One};

src/coreclr/jit/codegenarmarch.cpp

@@ -759,6 +759,32 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);
  break;
 
+#ifdef TARGET_ARM
+ case NI_PRIMITIVE_SaturateToInt8:
+ // SSAT Rd, #8, Rn - saturate int32 to signed 8-bit range [-128, 127]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToInt16:
+ // SSAT Rd, #16, Rn - saturate int32 to signed 16-bit range [-32768, 32767]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_ssat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt8:
+ // USAT Rd, #8, Rn - saturate int32 to unsigned 8-bit range [0, 255]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 8);
+ break;
+
+ case NI_PRIMITIVE_SaturateToUInt16:
+ // USAT Rd, #16, Rn - saturate int32 to unsigned 16-bit range [0, 65535]
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_I_I(INS_usat, EA_4BYTE, treeNode->GetRegNum(), srcNode->GetRegNum(), 0, 16);
+ break;
+#endif // TARGET_ARM
+
 #if defined(FEATURE_SIMD)
  // The handling is a bit more complex so genSimdUpperSave/Restore
  // handles genConsumeOperands and genProduceReg

src/coreclr/jit/codegenloongarch64.cpp

@@ -4444,7 +4444,94 @@ void CodeGen::genEmitGSCookieCheck(bool tailCall)
 //
 void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
 {
- NYI("unimplemented on LOONGARCH64 yet");
+ GenTree* op1 = treeNode->gtGetOp1();
+ GenTree* op2 = treeNode->gtGetOp2IfPresent();
+
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction FP pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `slli.w rd, rs, 0` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R_I(INS_slli_w, EA_4BYTE, dst, src, 0);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
+ emitAttr attr = emitActualTypeSize(treeNode);
+ instruction instr;
+
+ // All remaining intrinsics are binary floating-point operations.
+ assert(op2 != nullptr);
+
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_System_Math_MaxNative:
+ instr = (attr == EA_4BYTE) ? INS_fmax_s : INS_fmax_d;
+ break;
+ case NI_System_Math_MinNative:
+ instr = (attr == EA_4BYTE) ? INS_fmin_s : INS_fmin_d;
+ break;
+ default:
+ NO_WAY("Unknown intrinsic");
+ }
+ genConsumeOperands(treeNode->AsOp());
+ GetEmitter()->emitIns_R_R_R(instr, attr, treeNode->GetRegNum(), op1->GetRegNum(), op2->GetRegNum());
+ genProduceReg(treeNode);
 }
 
 //---------------------------------------------------------------------

src/coreclr/jit/codegenriscv64.cpp

@@ -4218,6 +4218,71 @@ void CodeGen::genIntrinsic(GenTreeIntrinsic* treeNode)
  GenTree* op1 = treeNode->gtGetOp1();
  GenTree* op2 = treeNode->gtGetOp2IfPresent();
 
+ // Handle integer-domain saturation intrinsics separately; they use branches
+ // and a temporary register rather than the single-instruction pattern below.
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+ ssize_t minVal, maxVal;
+ switch (treeNode->gtIntrinsicName)
+ {
+ case NI_PRIMITIVE_SaturateToInt8:
+ minVal = INT8_MIN;
+ maxVal = INT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ minVal = INT16_MIN;
+ maxVal = INT16_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ minVal = 0;
+ maxVal = UINT8_MAX;
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ minVal = 0;
+ maxVal = UINT16_MAX;
+ break;
+ default:
+ unreached();
+ }
+
+ genConsumeOperands(treeNode->AsOp());
+ regNumber dst = treeNode->GetRegNum();
+ regNumber src = op1->GetRegNum();
+ regNumber tmpReg = internalRegisters.GetSingle(treeNode);
+ emitter* emit = GetEmitter();
+
+ // Copy src to dst, normalizing to a sign-extended 32-bit value so the
+ // subsequent full-register bge compares against the (signed) clamp bounds
+ // are well-defined. `sext.w rd, rs` sign-extends bits[31:0] into rd[63:0].
+ emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dst, src);
+
+ // Clamp lower bound: if dst < minVal, dst = minVal.
+ BasicBlock* skipLo = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, minVal);
+ emit->emitIns_J_cond_la(INS_bge, skipLo, dst, tmpReg); // skip if dst >= minVal
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = minVal
+ genDefineTempLabel(skipLo);
+
+ // Clamp upper bound: if dst > maxVal, dst = maxVal.
+ BasicBlock* skipHi = genCreateTempLabel();
+ instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, maxVal);
+ emit->emitIns_J_cond_la(INS_bge, skipHi, tmpReg, dst); // skip if maxVal >= dst
+ emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dst, tmpReg); // dst = maxVal
+ genDefineTempLabel(skipHi);
+
+ genProduceReg(treeNode);
+ return;
+ }
+
+ default:
+ break;
+ }
+
  emitAttr size = emitActualTypeSize(op1);
  bool is4 = (size == EA_4BYTE);
 

src/coreclr/jit/emitarm.cpp

@@ -3344,11 +3344,6 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  int msb = lsb + width - 1;
  int imm = 0; /* combined immediate */
 
- assert((lsb >= 0) && (lsb <= 31)); // required for encodings
- assert((width > 0) && (width <= 32)); // required for encodings
- assert((msb >= 0) && (msb <= 31)); // required for encodings
- assert(msb >= lsb); // required for encodings
-
  /* Figure out the encoding format of the instruction */
  switch (ins)
  {
@@ -3357,6 +3352,10 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | msb;
 
  fmt = IF_T2_D0;
@@ -3369,12 +3368,44 @@ void emitter::emitIns_R_R_I_I(instruction ins,
  assert(reg2 != REG_PC);
 
  assert(insDoesNotSetFlags(flags));
+ assert((lsb >= 0) && (lsb <= 31)); // required for encoding
+ assert((width > 0) && (width <= 32)); // required for encoding
+ assert((msb >= 0) && (msb <= 31)); // required for encoding
+ assert(msb >= lsb); // required for encoding
  imm = (lsb << 5) | (width - 1);
 
  fmt = IF_T2_D0;
  sf = INS_FLAGS_NOT_SET;
  break;
 
+ case INS_ssat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (1-32)
+ // Encoding: sat_imm field = N-1 stored in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 1) && (imm2 <= 32)); // required for encoding
+ imm = (lsb << 5) | (width - 1); // lsb=shift=0, width=N -> sat_imm = N-1
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
+ case INS_usat:
+ // imm1 = shift amount (must be 0 for no shift), imm2 = saturation bits N (0-31)
+ // Encoding: sat_imm field = N stored directly in bits[4:0]; no shift (sh=0, imm5=0).
+ assert(reg1 != REG_PC); // VM debugging single stepper doesn't support PC register with this instruction.
+ assert(reg2 != REG_PC);
+
+ assert(insDoesNotSetFlags(flags));
+ assert((imm1 == 0) && (imm2 >= 0) && (imm2 <= 31)); // required for encoding
+ imm = (lsb << 5) | width; // lsb=shift=0, width=N -> sat_imm = N
+
+ fmt = IF_T2_D0;
+ sf = INS_FLAGS_NOT_SET;
+ break;
+
  default:
  unreached();
  }
@@ -7569,6 +7600,18 @@ void emitter::emitDispInsHelp(
  emitDispImm(imm1, true);
  emitDispImm(imm2, false);
  }
+ else if (ins == INS_ssat)
+ {
+ // SSAT: stored as sat_imm = N-1; display as #N (saturation bits)
+ int satBits = (imm & 0x1f) + 1;
+ emitDispImm(satBits, false);
+ }
+ else if (ins == INS_usat)
+ {
+ // USAT: stored as sat_imm = N; display as #N (saturation bits)
+ int satBits = imm & 0x1f;
+ emitDispImm(satBits, false);
+ }
  else
  {
  int lsb = (imm >> 5) & 0x1f;

src/coreclr/jit/gentree.cpp

@@ -6796,6 +6796,26 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
 #endif
  }
 
+ case NI_PRIMITIVE_SaturateToInt8:
+ case NI_PRIMITIVE_SaturateToInt16:
+ case NI_PRIMITIVE_SaturateToUInt8:
+ case NI_PRIMITIVE_SaturateToUInt16:
+ {
+#if defined(TARGET_ARM)
+ // Single SSAT/USAT instruction.
+ costEx = 1;
+ costSz = 4;
+#else
+ // Targets without saturating ALU ops (e.g. RISC-V64, LoongArch64)
+ // expand this into a normalize, two bound materializations, and two
+ // compare/branch/move pairs (~7 instructions), so it is materially
+ // more expensive.
+ costEx = 7;
+ costSz = 28;
+#endif
+ break;
+ }
+
  case NI_System_Math_Acos:
  case NI_System_Math_Acosh:
  case NI_System_Math_Asin:
@@ -7249,7 +7269,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
  level++;
  break;
  }
-#endif // TARGET_RISCV64
+#elif defined(TARGET_WASM)
+ // WASM lowers MaxNative/MinNative to native min/max instructions. Used
+ // both by user calls and by morph's float -> small int saturating clamp.
+ case NI_System_Math_MaxNative:
+ case NI_System_Math_MinNative:
+ {
+ level++;
+ break;
+ }
+#endif // TARGET_RISCV64 || TARGET_WASM
 
  default:
  assert(!"Unknown binary GT_INTRINSIC operator");
@@ -14245,6 +14274,18 @@ void Compiler::gtDispTree(GenTree* tree,
  printf(" popCount");
  break;
 #endif // TARGET_RISCV64
+ case NI_PRIMITIVE_SaturateToInt8:
+ printf(" saturateToInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToInt16:
+ printf(" saturateToInt16");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt8:
+ printf(" saturateToUInt8");
+ break;
+ case NI_PRIMITIVE_SaturateToUInt16:
+ printf(" saturateToUInt16");
+ break;
  case NI_System_Math_Pow:
  printf(" pow");
  break;