[RyuJIT Wasm] Handle all codegen cases for PackedSimd.Shuffle

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

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[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

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Azure Pipelines:
Successfully started running 5 pipeline(s).
10 pipeline(s) were filtered out due to trigger conditions.
There may be pipelines that require an authorized user to comment /azp run to run.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

[azure-pipelines]

Azure Pipelines:
Successfully started running 5 pipeline(s).
10 pipeline(s) were filtered out due to trigger conditions.
There may be pipelines that require an authorized user to comment /azp run to run.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

[azure-pipelines]

Azure Pipelines:
Successfully started running 5 pipeline(s).
10 pipeline(s) were filtered out due to trigger conditions.
There may be pipelines that require an authorized user to comment /azp run to run.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

[azure-pipelines]

Azure Pipelines:
Successfully started running 5 pipeline(s).
10 pipeline(s) were filtered out due to trigger conditions.
There may be pipelines that require an authorized user to comment /azp run to run.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

[azure-pipelines]

Azure Pipelines:
Successfully started running 5 pipeline(s).
10 pipeline(s) were filtered out due to trigger conditions.
There may be pipelines that require an authorized user to comment /azp run to run.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

[azure-pipelines]

Azure Pipelines:
Successfully started running 5 pipeline(s).
10 pipeline(s) were filtered out due to trigger conditions.
There may be pipelines that require an authorized user to comment /azp run to run.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}

[adamperlin]

This is fallback codgen in lowering for if we encounter PackedSimd.Shuffle(v1, v2, non_const_mask). We transform this into:

Or( Swizzle(v1, non_const_mask)
Swizzle(v2, (non_const_mask - 16))
)

This works because the range for the mask in shuffle should be [0, 31], whereas swizzle simply writes zero for any index not in [0, 15]. So, the original mask selects elements from the first vector, and the modified mask - 16 truncates any indices which correspond to the first vector to be out of range, allowing for selection from the second vector.

PackedSimd.Shuffle is internal to System.Private.CoreLib, so it's not part of the public API surface but we do need to handle it to build System.Private.CoreLib.

[azure-pipelines]

Azure Pipelines:
Successfully started running 5 pipeline(s).
10 pipeline(s) were filtered out due to trigger conditions.
There may be pipelines that require an authorized user to comment /azp run to run.

[dotnet-policy-service]

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

[Copilot]

Pull request overview

Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.

Changes:

• Add LowerHWIntrinsicNativeShuffle to support NI_PackedSimd_Shuffle (emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or).
• Introduce HW_Flag_HasImmediateOperand for WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment).
• Reclassify/enable WASM lane load/store intrinsics as HW_Category_MemoryLoad/MemoryStore and update codegen + OperIsMemoryLoad/Store to recognize WASM.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/coreclr/jit/lowerwasm.cpp	Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment.
src/coreclr/jit/lower.h	Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle.
src/coreclr/jit/hwintrinsicwasm.cpp	Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops.
src/coreclr/jit/hwintrinsiclistwasm.h	Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics.
src/coreclr/jit/hwintrinsiccodegenwasm.cpp	Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops.
src/coreclr/jit/hwintrinsic.h	Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor.
src/coreclr/jit/gentree.cpp	Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM.
src/coreclr/jit/codegenwasm.cpp	Removes NYI guard for SIMD16 store-indirect to allow emitting stores.

[Copilot]

Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.

[Copilot]

Pull request overview

Copilot reviewed 7 out of 7 changed files in this pull request and generated 6 comments.

Comments suppressed due to low confidence (1)

src/tests/JIT/HardwareIntrinsics/Wasm/PackedSimd/PackedSimdTests.cs:1085

• This test was disabled by commenting it out, which drops coverage for null-check behavior of these load/store intrinsics. If it’s flaky or platform-dependent, it should be guarded with an appropriate conditional attribute; otherwise it should remain enabled.

 // [Fact]
// public static unsafe void LoadStoreNullCheckTest()
// {
// Assert.Throws<NullReferenceException>(() => LoadScalarAndSplatVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadWideningVector128(null));
// Assert.Throws<NullReferenceException>(() => LoadScalarAndInsert(null, 2));
// Assert.Throws<NullReferenceException>(() => StoreSelectedScalar(null, 2));
// }

[Copilot]

Pull request overview

Copilot reviewed 6 out of 6 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/lowerwasm.cpp:1402

• This comment uses an incorrect exception name (ArrayIndexOutOfBoundsException) and also describes the check as GreaterThanAny(mask, 31), while the actual behavior is a ">= 32" range check that throws the runtime's range-check exception. Please align the comment with the actual condition and exception type used.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (2)

src/coreclr/jit/lowerwasm.cpp:1381

• This comment block says the bounds-check uses CNS_INT int 31, but the actual code below builds gtNewIconNode(32) and codegen checks mask >= bound (so 32 is the correct bound). Updating the comment will avoid confusion when debugging LIR dumps.

 // m0 = * LCL_VAR originalMaskTmp
// b0 = * CNS_INT int 32
// /--* m0 simd
// +--* b0 int
// GT_BOUNDS_CHECK RNG_CHK_FAIL

src/coreclr/jit/lowerwasm.cpp:1403

• The pseudo-C# uses ArrayIndexOutOfBoundsException, which isn’t a .NET exception type, and it references a bound of 31 while the implementation uses >= 32. Since this comment is describing the exact semantics of the inserted GT_BOUNDS_CHECK, it should match the code more directly.

 // This is roughly equivalent to the following C#:
// ...
// if (GreaterThanAny(originalMask, 31)) { throw new ArrayIndexOutOfBoundsException(); }
// tmp1 = PackedSimd.Swizzle(op1, originalMask);
// tmp2 = PackedSimd.Swizzle(op2, PackedSimd.Subtract(originalMask, PackedSimd.Splat(0x10)));

[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated no new comments.

Comments suppressed due to low confidence (1)

src/coreclr/jit/codegenwasm.cpp:2287

• genRangeCheck treats any SIMD-typed GT_BOUNDS_CHECK index as a byte-vector mask and emits i8x16.* ops unconditionally. That assumption is only valid for the new shuffle-mask bounds check (SCK_ARG_RNG_EXCPN) and could silently miscompile any future bounds checks that use SIMD indices with non-byte lane semantics. Consider restricting the SIMD path to the specific throw kind / expected shape, and assert the length operand is an int scalar.

#ifdef FEATURE_SIMD
if (varTypeIsSIMD(boundsCheck->GetIndex()->TypeGet()))
{
GetEmitter()->emitIns(INS_i8x16_splat);
GetEmitter()->emitIns(INS_i8x16_ge_u);
GetEmitter()->emitIns(INS_v128_any_true);
}
else
#endif
{
GetEmitter()->emitIns(INS_I_ge_u);
}