[Arm64] AdvSIMD LoadPairVector64 and LoadPairVector128 by echesakov · Pull Request #45020 · dotnet/runtime

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

echesakov · 2020-11-20T20:18:23Z

This is combined work:

based on Carol's changes in Support mulx returning ValueTuple #37928 (that originally were done as implementation of Bmi2 MultiplyNoFlags2) that adds support for hardware intrinsics returning their result in multiple registers and
my changes that affect Arm64 side of the JIT and implement LoadPairVector64 and LoadPairVector128 ([Arm64] LoadPairVector64 and LoadPairVector128 #39243).

Background: Based on our discussion with Carol we decided to include her changes that enable support for hardware intrinsics multiple registers return value in #37928 minus Bmi2.MultiplyNoFlags2 related changes (this would require an approval of #44926 in an API review meeting) as a part of this PR.

Fixes:#39243

Fixdotnet#11782

…formNotSupported.cs

…dvSimd.cs AdvSimd.PlatformNotSupported.cs

…otSupported.cs

…lr/src/jit/hwintrinsic.cpp

…lags

…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

…coreclr/src/jit/hwintrinsicarm64.cpp

…r/src/jit/hwintrinsiccodegenarm64.cpp

…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Dotnet-GitSync-Bot · 2020-11-20T20:18:27Z

Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

echesakov · 2020-11-20T20:22:31Z

 #endif
 }
 }
+ else if (src->OperIsHWIntrinsic())


@CarolEidt I think I need to implement a similar logic on Arm64 to avoid store-reload of returned SIMD values for ldp/ldnp as in the following example:
2C404410 ldnp s16, s17,[x0] FD000FB0 str d16,[fp,#24] FD0013B1 str d17,[fp,#32] FD400FA8 ldr d8,[fp,#24] FD4013A9 ldr d9,[fp,#32]
Is it correct understanding?

Yes, I believe that's correct. However, this path is only for the case where you wind up with a STORE_BLK, as opposed to a STORE_LCL_VAR. If the lhs is a multi-reg lclVar, you should have the latter.

ViktorHofer · 2020-12-08T14:50:55Z

// Auto-generated message

69e114c which was merged 12/7 removed the intermediate src/coreclr/src/ folder. This PR needs to be updated as it touches files in that directory which causes conflicts.

To update your commits you can use this bash script: https://gist.github.com/ViktorHofer/6d24f62abdcddb518b4966ead5ef3783. Feel free to use the comment section of the gist to improve the script for others.

ghost · 2021-01-25T13:01:42Z

Draft Pull Request was automatically closed for inactivity. It can be manually reopened in the next 30 days if the work resumes.

CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
d5aba6d

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

echesakov self-assigned this Nov 20, 2020

Dotnet-GitSync-Bot added the new-api-needs-documentation label Nov 20, 2020

echesakov commented Nov 20, 2020
View reviewed changes

echesakov mentioned this pull request Nov 20, 2020
[Arm64] Planned JIT work in .NET 6 #43629
Closed
29 tasks

ghost closed this Jan 25, 2021

ghost locked as resolved and limited conversation to collaborators Feb 24, 2021

echesakov deleted the Arm64-ASIMD-LoadPairVector64-LoadPairVector128 branch April 16, 2021 23:54

This pull request was closed.

CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
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echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

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[Arm64] Planned JIT work in .NET 6 #43629
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CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
d5aba6d

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

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[Arm64] Planned JIT work in .NET 6 #43629
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echesakov deleted the Arm64-ASIMD-LoadPairVector64-LoadPairVector128 branch April 16, 2021 23:54

This pull request was closed.

CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
d5aba6d

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

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[Arm64] Planned JIT work in .NET 6 #43629
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ghost closed this Jan 25, 2021

ghost locked as resolved and limited conversation to collaborators Feb 24, 2021

echesakov deleted the Arm64-ASIMD-LoadPairVector64-LoadPairVector128 branch April 16, 2021 23:54

This pull request was closed.

CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
d5aba6d

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

echesakov self-assigned this Nov 20, 2020

Dotnet-GitSync-Bot added the new-api-needs-documentation label Nov 20, 2020

echesakov commented Nov 20, 2020
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echesakov mentioned this pull request Nov 20, 2020
[Arm64] Planned JIT work in .NET 6 #43629
Closed
29 tasks

ghost closed this Jan 25, 2021

ghost locked as resolved and limited conversation to collaborators Feb 24, 2021

echesakov deleted the Arm64-ASIMD-LoadPairVector64-LoadPairVector128 branch April 16, 2021 23:54

This pull request was closed.

CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
d5aba6d

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

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echesakov commented Nov 20, 2020
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[Arm64] Planned JIT work in .NET 6 #43629
Closed
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ghost closed this Jan 25, 2021

ghost locked as resolved and limited conversation to collaborators Feb 24, 2021

echesakov deleted the Arm64-ASIMD-LoadPairVector64-LoadPairVector128 branch April 16, 2021 23:54

This pull request was closed.

CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
d5aba6d

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

echesakov self-assigned this Nov 20, 2020

Dotnet-GitSync-Bot added the new-api-needs-documentation label Nov 20, 2020

echesakov commented Nov 20, 2020
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echesakov mentioned this pull request Nov 20, 2020
[Arm64] Planned JIT work in .NET 6 #43629
Closed
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ghost closed this Jan 25, 2021

ghost locked as resolved and limited conversation to collaborators Feb 24, 2021

echesakov deleted the Arm64-ASIMD-LoadPairVector64-LoadPairVector128 branch April 16, 2021 23:54

This pull request was closed.

CarolEidtand others added 18 commits November 18, 2020 19:23

Support mulx returning ValueTuple
cbd01ca
Fixdotnet#11782

Remove accidentially added build.out build-tests.out libs.out
7445ac0

Add LoadPairVector64 and LoadPairVector128 in AdvSimd.cs AdvSimd.Plat…
a39417c
…formNotSupported.cs

Add LoadPairScalarVector64 in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
5c200a0

Add LoadPairVector64NonTemporal and LoadPairVector128NonTemporal in A…
41fda0d
…dvSimd.cs AdvSimd.PlatformNotSupported.cs

Add LoadPairScalarVector64NonTemporal in AdvSimd.cs AdvSimd.PlatformN…
b1ba848
…otSupported.cs

Update System.Runtime.Intrinsics.cs
c662e7f

Add LoadPairVector64 and LoadPairVector128 in hwintrinsiclistarm64.h
3608e63

Support LoadPairVector128/64 in Compiler::impHWIntrinsic in src/corec…
3f1f20a
…lr/src/jit/hwintrinsic.cpp

Exclude changes affecting current code generation of Bmi2.MultiplyNoF…
8873f70
…lags

Support multireg hardware intrinsics on Arm64 in src/coreclr/src/jit/…
a69244e
…gentree.cpp src/coreclr/src/jit/gentree.h src/coreclr/src/jit/lsra.cpp

Support LoadPairVector128/64 in Compiler::impSpecialIntrinsic in src/…
7b51ee7
…coreclr/src/jit/hwintrinsicarm64.cpp

Support LoadPairVector128/64 in CodeGen::genHWIntrinsic in src/corecl…
9828c6e
…r/src/jit/hwintrinsiccodegenarm64.cpp

Extend LinearScan::BuildHWIntrinsic to support intrinsics returning v…
b20717f
…alues in multiple registers in src/coreclr/src/jit/lsra.h src/coreclr/src/jit/lsraarm64.cpp src/coreclr/src/jit/lsraxarch.cpp

Add LoadPairVectorTest.template
e6cb0d3

Add LoadPairVector64 and LoadPairVector128 in GenerateTests.csx
4d808e3

Add .Take() in src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs…
3b97de6
… src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt

Update src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/*
d5aba6d

echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 20, 2020

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Dotnet-GitSync-Bot added the new-api-needs-documentation label Nov 20, 2020

echesakov commented Nov 20, 2020
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[Arm64] Planned JIT work in .NET 6 #43629
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echesakov deleted the Arm64-ASIMD-LoadPairVector64-LoadPairVector128 branch April 16, 2021 23:54

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