Arm64: addressing modes

[EgorBo]

draft pr. The goal is to achieve this codegen: https://godbolt.org/z/dEerMoE6M
when we access any C# array by index (variable).
Currently JIT emits for it:

 mov w1, w1 ;; zero extend for index.
lsl x1, x1, #2
add x1, x1, #16
ldr w0, [x0, x1]

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Issue Details

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draft pr

Author:	EgorBo
Assignees:	-
Labels:	area-CodeGen-coreclr
Milestone:	-

[BruceForstall]

Incorporating to godbolt data here, you suggest generating:

 add x8, x0, w1, sxtw #2
ldr w0, [x8, #12]

One issue with this form is that we'll always need two instructions inside a loop; if w1 is the loop array index, neither instruction is hoistable.

#35618 suggested a form of generating array base + data offset (as a byref), which is hoistable out of a loop, and then generating ldr w0, [x0, w1, sxtw #2] in the loop body, so you only have one instruction in the loop.

[EgorBo]

Incorporating to godbolt data here, you suggest generating:

 add x8, x0, w1, sxtw #2
ldr w0, [x8, #12]

One issue with this form is that we'll always need two instructions inside a loop; if w1 is the loop array index, neither instruction is hoistable.

#35618 suggested a form of generating array base + data offset (as a byref), which is hoistable out of a loop, and then generating ldr w0, [x0, w1, sxtw #2] in the loop body, so you only have one instruction in the loop.

Thanks, Bruce, yeah I keep that in mind. Actually it can be easily enabled even today in fgMorphArrayIndex. Currently we morph GT_INDEX into
(baseRef + ((indexRef * scaleCns) + dataOffsetCns)
while we can change it to
((baseRef + dataOffsetCns) + (indexRef * scaleCns)) if it's safe from GC's point of view and then (baseRef + dataOffsetCns) will be hoisted.

Alternatively, we can implement a more generic optimization for patterns like this:

"(invariantTree1 + X) + invariantTree2" => "X + (invariantTree1 + invariantTree2)"