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Ensure that GT_CNS_VEC is handled in LinearScan::isMatchingConstant - #70171

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Jun 3, 2022
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Ensure that GT_CNS_VEC is handled in LinearScan::isMatchingConstant#70171
tannergooding merged 3 commits into
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tannergooding:vector-cns

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This is a small follow up to #68874 but provides decent improvements, particularly where the same constant (Zero and AllBitsSet in particular) is repeatedly used.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 2, 2022
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ghost commented Jun 2, 2022

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Issue Details

This is a small follow up to #68874 but provides decent improvements, particularly where the same constant (Zero and AllBitsSet in particular) is repeatedly used.

Author:tannergooding
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Looks good and easy change.

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Example diffs

Note that ymm7 is set to "all bits set" first, and then reused on the last line rather than also using ymm6

 vpcmpeqd ymm7, ymm7, ymm7
vxorps ymm6, ymm7, ymm6
vcmpps ymm4, ymm4, ymm0, 0
vorps ymm4, ymm4, ymm6
- vpcmpeqd ymm6, ymm6, ymm6- vpcmpeqd ymm4, ymm4, ymm6+ vpcmpeqd ymm4, ymm4, ymm7

Note how ymm2 isn't reloaded with reloc @RDW00 because it was already in ymm2:

 vmovupd ymm2, ymmword ptr[reloc @RWD00]
vpshufb ymm0, ymm0, ymm2
vperm2i128 ymm0, ymm0, ymm0, 1
- vmovupd ymm2, ymmword ptr[reloc @RWD00]
vpshufb ymm1, ymm1, ymm2

case GT_CNS_INT:
case GT_CNS_LNG:
case GT_CNS_DBL:
case GT_CNS_VEC:

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Noting ARM64 already had a path here since it needed special handling for Zero and AllBitsSet, it just wasn't getting used in LSRA

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@kunalspathak could you take a look? Its super small (8 lines) but touches LSRA so I'd appreciate your sign-off as well.

@kunalspathakkunalspathak left a comment

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LGTM

Comment threadsrc/coreclr/jit/codegenarmarch.cpp Outdated
Co-authored-by: Egor Bogatov <egorbo@gmail.com>
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@tannergooding@EgorBo@TIHan@kunalspathak