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Transform IntCon(0) to VecCon(0) for WithElement case - fixes emitter assertion for crossgen2 - #81981

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TIHan merged 2 commits into
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TIHan:hw-vec-con-zero-fix
Feb 11, 2023
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Transform IntCon(0) to VecCon(0) for WithElement case - fixes emitter assertion for crossgen2#81981
TIHan merged 2 commits into
dotnet:mainfrom
TIHan:hw-vec-con-zero-fix

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@TIHan

@TIHanTIHan commented Feb 10, 2023

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Fixes#81963
This fixes the assertion that was occurring in the emitter recently.
Thanks to @tannergooding for his help on this.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Feb 10, 2023
@ghostghost assigned TIHanFeb 10, 2023
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Author:TIHan
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area-CodeGen-coreclr

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/azp run runtime-coreclr outerloop

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Azure Pipelines successfully started running 1 pipeline(s).

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/azp run runtime-coreclr outerloop

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// If we are not doing struct promotion and we have zero-initialization,
// then we need to produce a VecCon(0).
if (elementNode->IsIntegralConst(0))

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Just wanted to note that we looked at fixing CEE_INITOBJ to do have TYP_SIMD be an ASG of ZeroConNode like it is for primitives

But, it still asserted so there are likely other places also introducing the ASG = 0 that would also need to be fixed first.

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@dotnet/jit-contrib this is ready and appears to fix the assertion based on the outerloop run.

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TIHan merged commit 38e660d into dotnet:mainFeb 11, 2023
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TIHan deleted the hw-vec-con-zero-fix branch February 11, 2023 04:30
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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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Successfully merging this pull request may close these issues.

Crossgen2 asserts in JIT when compiling The JIT\Regression\JitBlue\Runtime_81739

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@TIHan@tannergooding@BruceForstall