Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
khushal1996 wants to merge 13 commits into from
Closed

Isolating JITDbl2Ulng helper changes #86175

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
13 commits
Select commit Hold shift + click to select a range
7bae37a
fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…
khushal1996 May 9, 2023
73dc4c4
Making changes to the library test case expected output based on the …
khushal1996 May 10, 2023
fbc134d
Fixing the JITDbl2Ulng helper function. Also making sure that we are …
khushal1996 May 12, 2023
293e84d
reverting jitformat
khushal1996 May 12, 2023
6d14c22
Adding a truncate function to the Dbl2Ulng helper to make sure we avo…
khushal1996 May 15, 2023
d977447
Adding code to handle vectorized conversion for float/double to/from …
khushal1996 May 16, 2023
0845905
reverting changes for float to ulong
khushal1996 May 16, 2023
451780e
enabling float to ulong conversion
khushal1996 May 16, 2023
06ecf6a
Making change to set w1 bit for evex
khushal1996 May 17, 2023
6b963e6
trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…
khushal1996 May 18, 2023
e8f06d9
jit format
khushal1996 May 18, 2023
c703c1b
Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…
khushal1996 May 18, 2023
bb4a91e
undoing jitformat changes due to merge error
khushal1996 May 18, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 17 additions & 3 deletions src/coreclr/jit/codegenxarch.cpp
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
noway_assert(srcType != TYP_UINT);
noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
{
if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
{
genConsumeOperands(treeNode->AsOp());
instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
genProduceReg(treeNode);
return;
}
}

// To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
// which does a partial write to lower 4/8 bytes of xmm register keeping the other
// upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

// We shouldn't be seeing uint64 here as it should have been converted
// into a helper call by either front-end or lowering phase.
noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
// into a helper call by either front-end or lowering phase, unless we have AVX512F
// accelerated conversions.
noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

// If the dstType is TYP_UINT, we have 32-bits to encode the
// float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
// Note that we need to specify dstType here so that it will determine
// the size of destination integer register and also the rex.w prefix.
genConsumeOperands(treeNode->AsOp());
instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
genProduceReg(treeNode);
}
Expand Down
9 changes: 9 additions & 0 deletions src/coreclr/jit/emit.h
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
return EA_32BYTE;
}

case INS_vcvttss2usi64:
{
if (defaultSize == 8)
{
return EA_4BYTE;
}
return defaultSize;
}

case INS_movddup:
{
if (defaultSize == 64)
Expand Down
35 changes: 29 additions & 6 deletions src/coreclr/jit/emitxarch.cpp
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
case INS_vcvtsd2usi:
case INS_vcvtss2usi:
case INS_vcvttsd2usi:
case INS_vcvttss2usi:
{
if (attr == EA_8BYTE)
{
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
case INS_vcvtsd2usi:
case INS_vcvtss2usi:
case INS_vcvttsd2usi:
case INS_vcvttss2usi:
case INS_vcvttss2usi32:
case INS_vcvttss2usi64:
{
// These SSE instructions write to a general purpose integer register.
return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
case INS_vcvtsd2usi:
case INS_vcvtss2usi:
case INS_vcvttsd2usi:
case INS_vcvttss2usi:
{
printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
break;
}

case INS_vcvttss2usi32:
case INS_vcvttss2usi64:
{
printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
break;
}

#ifdef TARGET_AMD64
case INS_movsxd:
{
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
case INS_cvtsi2sd64:
case INS_cvtsi2ss64:
case INS_vcvtsd2usi:
case INS_vcvttsd2usi:
case INS_vcvtusi2sd32:
case INS_vcvtusi2sd64:
case INS_vcvtusi2ss32:
case INS_vcvtusi2ss64:
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
result.insLatency += PERFSCORE_LATENCY_7C;
break;

case INS_vcvttsd2usi:
result.insLatency += PERFSCORE_LATENCY_6C;
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
break;

case INS_vcvtusi2sd64:
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
result.insLatency += PERFSCORE_LATENCY_5C;
break;

case INS_cvttss2si:
case INS_cvtss2si:
case INS_vcvtss2usi:
case INS_vcvttss2usi:
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
break;

case INS_vcvttss2usi32:
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
result.insLatency += PERFSCORE_LATENCY_7C;
break;

case INS_vcvttss2usi64:
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
result.insLatency += PERFSCORE_LATENCY_8C;
break;

case INS_cvtss2sd:
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/jit/hwintrinsiclistxarch.h
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down
16 changes: 16 additions & 0 deletions src/coreclr/jit/instr.cpp
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
// AVX: For now we support only conversion from Int/Long -> float
// AVX512: Supports following conversions
// srcType = float/double castToType = ulong
// srcType = ulong castToType = double

switch (from)
{
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
return ins_Move_Extend(TYP_FLOAT, false);
case TYP_DOUBLE:
return INS_cvtss2sd;
case TYP_ULONG:
return INS_vcvttss2usi64;
default:
unreached();
}
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
return INS_cvttsd2si;
case TYP_LONG:
return INS_cvttsd2si;
case TYP_ULONG:
return INS_vcvttsd2usi;
case TYP_FLOAT:
return INS_cvtsd2ss;
case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
}
break;

case TYP_ULONG:
switch (to)
{
case TYP_DOUBLE:
return INS_vcvtusi2sd64;
default:
unreached();
}

default:
unreached();
}
Expand Down
3 changes: 2 additions & 1 deletion src/coreclr/jit/instrsxarch.h
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/lowerxarch.cpp
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
// srcType = float/double castToType = * and overflow detecting cast
// Reason: must be converted to a helper call
// srcType = float/double, castToType = ulong
// Reason: must be converted to a helper call
// Reason: must be converted to a helper call unless we have AVX512F
// srcType = uint castToType = float/double
// Reason: uint -> float/double = uint -> long -> float/double
// srcType = ulong castToType = float
// Reason: ulong -> float = ulong -> double -> float
if (varTypeIsFloating(srcType))
if (srcType == TYP_FLOAT)
{
noway_assert(!tree->gtOverflow());
noway_assert(castToType != TYP_ULONG);
noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
}
else if (srcType == TYP_UINT)
{
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/morph.cpp
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

case TYP_ULONG:
#ifdef TARGET_AMD64
if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
return nullptr;
#endif
return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
default:
unreached();
Expand Down
Loading
, 'i'); if (__m === '*' || __re.test(location.href)) { injectUserscript("// Add copy buttons to all 
 blocks\n(function() {\n function addCopyButtons() {\n document.querySelectorAll('pre code').forEach(function(codeBlock) {\n if (codeBlock.parentElement.hasAttribute('data-copy-added')) return;\n codeBlock.parentElement.setAttribute('data-copy-added', 'true');\n \n var btn = document.createElement('button');\n btn.textContent = 'Copy';\n btn.style.cssText = 'position:absolute;top:4px;right:4px;padding:2px 8px;font-size:11px;background:#4ecdc4;border:none;border-radius:4px;color:#1a1a2e;cursor:pointer;opacity:0.7;transition:opacity 0.2s;';\n btn.onmouseover = function() { this.style.opacity = '1'; };\n btn.onmouseout = function() { this.style.opacity = '0.7'; };\n btn.onclick = function() {\n navigator.clipboard.writeText(codeBlock.textContent).then(function() {\n btn.textContent = 'Copied!';\n setTimeout(function() { btn.textContent = 'Copy'; }, 1500);\n });\n };\n codeBlock.parentElement.style.position = 'relative';\n codeBlock.parentElement.appendChild(btn);\n });\n }\n \n addCopyButtons();\n \n // Re-run on dynamic content\n var observer = new MutationObserver(addCopyButtons);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Add Copy Buttons to Code Blocks");
}
} catch(__e) { console.warn('[Userscript:Add Copy Buttons to Code Blocks]', __e); }
})();
(function(){
try {
var __m = "github.com";
var __re = new RegExp('^' + "github\\.com" + '

Skip to content
Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and
privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Closed

khushal1996
wants to merge
13
commits into

from

 Closed


Isolating JITDbl2Ulng helper changes
#86175
Show file tree
Hide file tree
 Changes from all commits
Commits

Show all changes


13 commits


Select commit
Hold shift + click to select a range
7bae37a

fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…


khushal1996 May 9, 2023
73dc4c4

Making changes to the library test case expected output based on the …


khushal1996 May 10, 2023
fbc134d

Fixing the JITDbl2Ulng helper function. Also making sure that we are …


khushal1996 May 12, 2023
293e84d

reverting jitformat


khushal1996 May 12, 2023
6d14c22

Adding a truncate function to the Dbl2Ulng helper to make sure we avo…


khushal1996 May 15, 2023
d977447

Adding code to handle vectorized conversion for float/double to/from …


khushal1996 May 16, 2023
0845905

reverting changes for float to ulong


khushal1996 May 16, 2023
451780e

enabling float to ulong conversion


khushal1996 May 16, 2023
06ecf6a

Making change to set w1 bit for evex


khushal1996 May 17, 2023
6b963e6

trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…


khushal1996 May 18, 2023
e8f06d9

jit format


khushal1996 May 18, 2023
c703c1b

Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…


khushal1996 May 18, 2023
bb4a91e

undoing jitformat changes due to merge error


khushal1996 May 18, 2023

File filter

Filter by extension
Filter by extension
Conversations

Failed to load comments. 
Loading
Jump to

Jump to file


Failed to load files. 
Loading
 Diff view

 Diff view


20 changes: 17 additions & 3 deletions
src/coreclr/jit/codegenxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
 noway_assert(srcType != TYP_UINT);
 noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

 if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 {
 if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
 {
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
 genProduceReg(treeNode);
 return;
 }
 }

 // To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
 // which does a partial write to lower 4/8 bytes of xmm register keeping the other
 // upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

 // We shouldn't be seeing uint64 here as it should have been converted
 // into a helper call by either front-end or lowering phase.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
 // into a helper call by either front-end or lowering phase, unless we have AVX512F
 // accelerated conversions.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
 compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

 // If the dstType is TYP_UINT, we have 32-bits to encode the
 // float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 // Note that we need to specify dstType here so that it will determine
 // the size of destination integer register and also the rex.w prefix.
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
 genProduceReg(treeNode);
}
Expand Down

9 changes: 9 additions & 0 deletions
src/coreclr/jit/emit.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
 return EA_32BYTE;
 }

 case INS_vcvttss2usi64:
 {
 if (defaultSize == 8)
 {
 return EA_4BYTE;
 }
 return defaultSize;
 }

 case INS_movddup:
 {
 if (defaultSize == 64)
Expand Down

35 changes: 29 additions & 6 deletions
src/coreclr/jit/emitxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 if (attr == EA_8BYTE)
 {
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 // These SSE instructions write to a general purpose integer register.
 return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
 break;
 }

 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
 break;
 }

#ifdef TARGET_AMD64
 case INS_movsxd:
 {
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
 case INS_cvtsi2sd64:
 case INS_cvtsi2ss64:
 case INS_vcvtsd2usi:
 case INS_vcvttsd2usi:
 case INS_vcvtusi2sd32:
 case INS_vcvtusi2sd64:
 case INS_vcvtusi2ss32:
 case INS_vcvtusi2ss64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttsd2usi:
 result.insLatency += PERFSCORE_LATENCY_6C;
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 break;

 case INS_vcvtusi2sd64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
 break;

 case INS_cvttss2si:
 case INS_cvtss2si:
 case INS_vcvtss2usi:
 case INS_vcvttss2usi:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi32:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_8C;
 break;

 case INS_cvtss2sd:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/hwintrinsiclistxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down

16 changes: 16 additions & 0 deletions
src/coreclr/jit/instr.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
 // AVX: For now we support only conversion from Int/Long -> float
 // AVX512: Supports following conversions
 // srcType = float/double castToType = ulong
 // srcType = ulong castToType = double

 switch (from)
 {
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return ins_Move_Extend(TYP_FLOAT, false);
 case TYP_DOUBLE:
 return INS_cvtss2sd;
 case TYP_ULONG:
 return INS_vcvttss2usi64;
 default:
 unreached();
 }
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return INS_cvttsd2si;
 case TYP_LONG:
 return INS_cvttsd2si;
 case TYP_ULONG:
 return INS_vcvttsd2usi;
 case TYP_FLOAT:
 return INS_cvtsd2ss;
 case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 }
 break;

 case TYP_ULONG:
 switch (to)
 {
 case TYP_DOUBLE:
 return INS_vcvtusi2sd64;
 default:
 unreached();
 }

 default:
 unreached();
 }
Expand Down

3 changes: 2 additions & 1 deletion
src/coreclr/jit/instrsxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/lowerxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
 // srcType = float/double castToType = * and overflow detecting cast
 // Reason: must be converted to a helper call
 // srcType = float/double, castToType = ulong
 // Reason: must be converted to a helper call
 // Reason: must be converted to a helper call unless we have AVX512F
 // srcType = uint castToType = float/double
 // Reason: uint -> float/double = uint -> long -> float/double
 // srcType = ulong castToType = float
 // Reason: ulong -> float = ulong -> double -> float
 if (varTypeIsFloating(srcType))
 if (srcType == TYP_FLOAT)
 {
 noway_assert(!tree->gtOverflow());
 noway_assert(castToType != TYP_ULONG);
 noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 }
 else if (srcType == TYP_UINT)
 {
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/jit/morph.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

 case TYP_ULONG:
#ifdef TARGET_AMD64
 if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 return nullptr;
#endif
 return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
 default:
 unreached();
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Force GitHub README to respect dark mode\n(function() {\n var style = document.createElement('style');\n style.textContent = '\n .markdown-body {\n color-scheme: dark light;\n }\n .markdown-body pre { background: #161b22 !important; }\n .markdown-body code { background: rgba(110, 118, 129, 0.4) !important; }\n .markdown-body table th, .markdown-body table td { border-color: #30363d !important; }\n .markdown-body img { background: #0d1117; }\n .markdown-body blockquote { border-left-color: #8b949e; }\n .markdown-body hr { border-color: #30363d; }\n ';\n document.head.appendChild(style);\n})();", "GitHub Dark Mode README Fix");
}
} catch(__e) { console.warn('[Userscript:GitHub Dark Mode README Fix]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and
privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Closed

khushal1996
wants to merge
13
commits into

from

 Closed


Isolating JITDbl2Ulng helper changes
#86175
Show file tree
Hide file tree
 Changes from all commits
Commits

Show all changes


13 commits


Select commit
Hold shift + click to select a range
7bae37a

fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…


khushal1996 May 9, 2023
73dc4c4

Making changes to the library test case expected output based on the …


khushal1996 May 10, 2023
fbc134d

Fixing the JITDbl2Ulng helper function. Also making sure that we are …


khushal1996 May 12, 2023
293e84d

reverting jitformat


khushal1996 May 12, 2023
6d14c22

Adding a truncate function to the Dbl2Ulng helper to make sure we avo…


khushal1996 May 15, 2023
d977447

Adding code to handle vectorized conversion for float/double to/from …


khushal1996 May 16, 2023
0845905

reverting changes for float to ulong


khushal1996 May 16, 2023
451780e

enabling float to ulong conversion


khushal1996 May 16, 2023
06ecf6a

Making change to set w1 bit for evex


khushal1996 May 17, 2023
6b963e6

trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…


khushal1996 May 18, 2023
e8f06d9

jit format


khushal1996 May 18, 2023
c703c1b

Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…


khushal1996 May 18, 2023
bb4a91e

undoing jitformat changes due to merge error


khushal1996 May 18, 2023

File filter

Filter by extension
Filter by extension
Conversations

Failed to load comments. 
Loading
Jump to

Jump to file


Failed to load files. 
Loading
 Diff view

 Diff view


20 changes: 17 additions & 3 deletions
src/coreclr/jit/codegenxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
 noway_assert(srcType != TYP_UINT);
 noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

 if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 {
 if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
 {
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
 genProduceReg(treeNode);
 return;
 }
 }

 // To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
 // which does a partial write to lower 4/8 bytes of xmm register keeping the other
 // upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

 // We shouldn't be seeing uint64 here as it should have been converted
 // into a helper call by either front-end or lowering phase.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
 // into a helper call by either front-end or lowering phase, unless we have AVX512F
 // accelerated conversions.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
 compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

 // If the dstType is TYP_UINT, we have 32-bits to encode the
 // float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 // Note that we need to specify dstType here so that it will determine
 // the size of destination integer register and also the rex.w prefix.
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
 genProduceReg(treeNode);
}
Expand Down

9 changes: 9 additions & 0 deletions
src/coreclr/jit/emit.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
 return EA_32BYTE;
 }

 case INS_vcvttss2usi64:
 {
 if (defaultSize == 8)
 {
 return EA_4BYTE;
 }
 return defaultSize;
 }

 case INS_movddup:
 {
 if (defaultSize == 64)
Expand Down

35 changes: 29 additions & 6 deletions
src/coreclr/jit/emitxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 if (attr == EA_8BYTE)
 {
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 // These SSE instructions write to a general purpose integer register.
 return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
 break;
 }

 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
 break;
 }

#ifdef TARGET_AMD64
 case INS_movsxd:
 {
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
 case INS_cvtsi2sd64:
 case INS_cvtsi2ss64:
 case INS_vcvtsd2usi:
 case INS_vcvttsd2usi:
 case INS_vcvtusi2sd32:
 case INS_vcvtusi2sd64:
 case INS_vcvtusi2ss32:
 case INS_vcvtusi2ss64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttsd2usi:
 result.insLatency += PERFSCORE_LATENCY_6C;
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 break;

 case INS_vcvtusi2sd64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
 break;

 case INS_cvttss2si:
 case INS_cvtss2si:
 case INS_vcvtss2usi:
 case INS_vcvttss2usi:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi32:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_8C;
 break;

 case INS_cvtss2sd:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/hwintrinsiclistxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down

16 changes: 16 additions & 0 deletions
src/coreclr/jit/instr.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
 // AVX: For now we support only conversion from Int/Long -> float
 // AVX512: Supports following conversions
 // srcType = float/double castToType = ulong
 // srcType = ulong castToType = double

 switch (from)
 {
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return ins_Move_Extend(TYP_FLOAT, false);
 case TYP_DOUBLE:
 return INS_cvtss2sd;
 case TYP_ULONG:
 return INS_vcvttss2usi64;
 default:
 unreached();
 }
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return INS_cvttsd2si;
 case TYP_LONG:
 return INS_cvttsd2si;
 case TYP_ULONG:
 return INS_vcvttsd2usi;
 case TYP_FLOAT:
 return INS_cvtsd2ss;
 case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 }
 break;

 case TYP_ULONG:
 switch (to)
 {
 case TYP_DOUBLE:
 return INS_vcvtusi2sd64;
 default:
 unreached();
 }

 default:
 unreached();
 }
Expand Down

3 changes: 2 additions & 1 deletion
src/coreclr/jit/instrsxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/lowerxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
 // srcType = float/double castToType = * and overflow detecting cast
 // Reason: must be converted to a helper call
 // srcType = float/double, castToType = ulong
 // Reason: must be converted to a helper call
 // Reason: must be converted to a helper call unless we have AVX512F
 // srcType = uint castToType = float/double
 // Reason: uint -> float/double = uint -> long -> float/double
 // srcType = ulong castToType = float
 // Reason: ulong -> float = ulong -> double -> float
 if (varTypeIsFloating(srcType))
 if (srcType == TYP_FLOAT)
 {
 noway_assert(!tree->gtOverflow());
 noway_assert(castToType != TYP_ULONG);
 noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 }
 else if (srcType == TYP_UINT)
 {
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/jit/morph.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

 case TYP_ULONG:
#ifdef TARGET_AMD64
 if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 return nullptr;
#endif
 return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
 default:
 unreached();
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Highlight search terms from Google/DuckDuckGo/Bing referrer\n(function() {\n var ref = document.referrer;\n var terms = [];\n \n if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {\n var url = new URL(ref);\n var q = url.searchParams.get('q') || url.searchParams.get('p');\n if (q) {\n terms = q.split(/\\s+/).filter(function(t) { return t.length > 2; });\n }\n }\n \n if (terms.length === 0) return;\n \n var style = document.createElement('style');\n style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';\n document.head.appendChild(style);\n \n function highlight(node) {\n if (node.nodeType === 3) { // text node\n var text = node.textContent;\n var found = false;\n terms.forEach(function(term) {\n var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\\]\\\\]/g, '\\\\') + ')', 'gi');\n if (regex.test(text)) {\n found = true;\n var frag = document.createDocumentFragment();\n var parts = text.split(regex);\n parts.forEach(function(part, i) {\n if (i % 2 === 0) {\n frag.appendChild(document.createTextNode(part));\n } else {\n var span = document.createElement('span');\n span.className = 'userscript-highlight';\n span.textContent = part;\n frag.appendChild(span);\n }\n });\n node.parentNode.replaceChild(frag, node);\n }\n });\n } else if (node.nodeType === 1 && node.childNodes) { // element\n var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];\n if (!skipTags.includes(node.tagName)) {\n Array.from(node.childNodes).forEach(highlight);\n }\n }\n }\n \n highlight(document.body);\n \n // Re-highlight on dynamic content\n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1 || node.nodeType === 3) highlight(node);\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Highlight Search Terms");
}
} catch(__e) { console.warn('[Userscript:Highlight Search Terms]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and
privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Closed

khushal1996
wants to merge
13
commits into

from

 Closed


Isolating JITDbl2Ulng helper changes
#86175
Show file tree
Hide file tree
 Changes from all commits
Commits

Show all changes


13 commits


Select commit
Hold shift + click to select a range
7bae37a

fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…


khushal1996 May 9, 2023
73dc4c4

Making changes to the library test case expected output based on the …


khushal1996 May 10, 2023
fbc134d

Fixing the JITDbl2Ulng helper function. Also making sure that we are …


khushal1996 May 12, 2023
293e84d

reverting jitformat


khushal1996 May 12, 2023
6d14c22

Adding a truncate function to the Dbl2Ulng helper to make sure we avo…


khushal1996 May 15, 2023
d977447

Adding code to handle vectorized conversion for float/double to/from …


khushal1996 May 16, 2023
0845905

reverting changes for float to ulong


khushal1996 May 16, 2023
451780e

enabling float to ulong conversion


khushal1996 May 16, 2023
06ecf6a

Making change to set w1 bit for evex


khushal1996 May 17, 2023
6b963e6

trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…


khushal1996 May 18, 2023
e8f06d9

jit format


khushal1996 May 18, 2023
c703c1b

Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…


khushal1996 May 18, 2023
bb4a91e

undoing jitformat changes due to merge error


khushal1996 May 18, 2023

File filter

Filter by extension
Filter by extension
Conversations

Failed to load comments. 
Loading
Jump to

Jump to file


Failed to load files. 
Loading
 Diff view

 Diff view


20 changes: 17 additions & 3 deletions
src/coreclr/jit/codegenxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
 noway_assert(srcType != TYP_UINT);
 noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

 if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 {
 if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
 {
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
 genProduceReg(treeNode);
 return;
 }
 }

 // To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
 // which does a partial write to lower 4/8 bytes of xmm register keeping the other
 // upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

 // We shouldn't be seeing uint64 here as it should have been converted
 // into a helper call by either front-end or lowering phase.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
 // into a helper call by either front-end or lowering phase, unless we have AVX512F
 // accelerated conversions.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
 compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

 // If the dstType is TYP_UINT, we have 32-bits to encode the
 // float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 // Note that we need to specify dstType here so that it will determine
 // the size of destination integer register and also the rex.w prefix.
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
 genProduceReg(treeNode);
}
Expand Down

9 changes: 9 additions & 0 deletions
src/coreclr/jit/emit.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
 return EA_32BYTE;
 }

 case INS_vcvttss2usi64:
 {
 if (defaultSize == 8)
 {
 return EA_4BYTE;
 }
 return defaultSize;
 }

 case INS_movddup:
 {
 if (defaultSize == 64)
Expand Down

35 changes: 29 additions & 6 deletions
src/coreclr/jit/emitxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 if (attr == EA_8BYTE)
 {
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 // These SSE instructions write to a general purpose integer register.
 return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
 break;
 }

 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
 break;
 }

#ifdef TARGET_AMD64
 case INS_movsxd:
 {
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
 case INS_cvtsi2sd64:
 case INS_cvtsi2ss64:
 case INS_vcvtsd2usi:
 case INS_vcvttsd2usi:
 case INS_vcvtusi2sd32:
 case INS_vcvtusi2sd64:
 case INS_vcvtusi2ss32:
 case INS_vcvtusi2ss64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttsd2usi:
 result.insLatency += PERFSCORE_LATENCY_6C;
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 break;

 case INS_vcvtusi2sd64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
 break;

 case INS_cvttss2si:
 case INS_cvtss2si:
 case INS_vcvtss2usi:
 case INS_vcvttss2usi:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi32:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_8C;
 break;

 case INS_cvtss2sd:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/hwintrinsiclistxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down

16 changes: 16 additions & 0 deletions
src/coreclr/jit/instr.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
 // AVX: For now we support only conversion from Int/Long -> float
 // AVX512: Supports following conversions
 // srcType = float/double castToType = ulong
 // srcType = ulong castToType = double

 switch (from)
 {
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return ins_Move_Extend(TYP_FLOAT, false);
 case TYP_DOUBLE:
 return INS_cvtss2sd;
 case TYP_ULONG:
 return INS_vcvttss2usi64;
 default:
 unreached();
 }
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return INS_cvttsd2si;
 case TYP_LONG:
 return INS_cvttsd2si;
 case TYP_ULONG:
 return INS_vcvttsd2usi;
 case TYP_FLOAT:
 return INS_cvtsd2ss;
 case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 }
 break;

 case TYP_ULONG:
 switch (to)
 {
 case TYP_DOUBLE:
 return INS_vcvtusi2sd64;
 default:
 unreached();
 }

 default:
 unreached();
 }
Expand Down

3 changes: 2 additions & 1 deletion
src/coreclr/jit/instrsxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/lowerxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
 // srcType = float/double castToType = * and overflow detecting cast
 // Reason: must be converted to a helper call
 // srcType = float/double, castToType = ulong
 // Reason: must be converted to a helper call
 // Reason: must be converted to a helper call unless we have AVX512F
 // srcType = uint castToType = float/double
 // Reason: uint -> float/double = uint -> long -> float/double
 // srcType = ulong castToType = float
 // Reason: ulong -> float = ulong -> double -> float
 if (varTypeIsFloating(srcType))
 if (srcType == TYP_FLOAT)
 {
 noway_assert(!tree->gtOverflow());
 noway_assert(castToType != TYP_ULONG);
 noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 }
 else if (srcType == TYP_UINT)
 {
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/jit/morph.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

 case TYP_ULONG:
#ifdef TARGET_AMD64
 if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 return nullptr;
#endif
 return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
 default:
 unreached();
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links");
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

Skip to content
Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and
privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Closed

khushal1996
wants to merge
13
commits into

from

 Closed


Isolating JITDbl2Ulng helper changes
#86175
Show file tree
Hide file tree
 Changes from all commits
Commits

Show all changes


13 commits


Select commit
Hold shift + click to select a range
7bae37a

fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…


khushal1996 May 9, 2023
73dc4c4

Making changes to the library test case expected output based on the …


khushal1996 May 10, 2023
fbc134d

Fixing the JITDbl2Ulng helper function. Also making sure that we are …


khushal1996 May 12, 2023
293e84d

reverting jitformat


khushal1996 May 12, 2023
6d14c22

Adding a truncate function to the Dbl2Ulng helper to make sure we avo…


khushal1996 May 15, 2023
d977447

Adding code to handle vectorized conversion for float/double to/from …


khushal1996 May 16, 2023
0845905

reverting changes for float to ulong


khushal1996 May 16, 2023
451780e

enabling float to ulong conversion


khushal1996 May 16, 2023
06ecf6a

Making change to set w1 bit for evex


khushal1996 May 17, 2023
6b963e6

trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…


khushal1996 May 18, 2023
e8f06d9

jit format


khushal1996 May 18, 2023
c703c1b

Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…


khushal1996 May 18, 2023
bb4a91e

undoing jitformat changes due to merge error


khushal1996 May 18, 2023

File filter

Filter by extension
Filter by extension
Conversations

Failed to load comments. 
Loading
Jump to

Jump to file


Failed to load files. 
Loading
 Diff view

 Diff view


20 changes: 17 additions & 3 deletions
src/coreclr/jit/codegenxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
 noway_assert(srcType != TYP_UINT);
 noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

 if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 {
 if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
 {
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
 genProduceReg(treeNode);
 return;
 }
 }

 // To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
 // which does a partial write to lower 4/8 bytes of xmm register keeping the other
 // upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

 // We shouldn't be seeing uint64 here as it should have been converted
 // into a helper call by either front-end or lowering phase.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
 // into a helper call by either front-end or lowering phase, unless we have AVX512F
 // accelerated conversions.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
 compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

 // If the dstType is TYP_UINT, we have 32-bits to encode the
 // float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 // Note that we need to specify dstType here so that it will determine
 // the size of destination integer register and also the rex.w prefix.
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
 genProduceReg(treeNode);
}
Expand Down

9 changes: 9 additions & 0 deletions
src/coreclr/jit/emit.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
 return EA_32BYTE;
 }

 case INS_vcvttss2usi64:
 {
 if (defaultSize == 8)
 {
 return EA_4BYTE;
 }
 return defaultSize;
 }

 case INS_movddup:
 {
 if (defaultSize == 64)
Expand Down

35 changes: 29 additions & 6 deletions
src/coreclr/jit/emitxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 if (attr == EA_8BYTE)
 {
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 // These SSE instructions write to a general purpose integer register.
 return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
 break;
 }

 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
 break;
 }

#ifdef TARGET_AMD64
 case INS_movsxd:
 {
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
 case INS_cvtsi2sd64:
 case INS_cvtsi2ss64:
 case INS_vcvtsd2usi:
 case INS_vcvttsd2usi:
 case INS_vcvtusi2sd32:
 case INS_vcvtusi2sd64:
 case INS_vcvtusi2ss32:
 case INS_vcvtusi2ss64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttsd2usi:
 result.insLatency += PERFSCORE_LATENCY_6C;
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 break;

 case INS_vcvtusi2sd64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
 break;

 case INS_cvttss2si:
 case INS_cvtss2si:
 case INS_vcvtss2usi:
 case INS_vcvttss2usi:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi32:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_8C;
 break;

 case INS_cvtss2sd:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/hwintrinsiclistxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down

16 changes: 16 additions & 0 deletions
src/coreclr/jit/instr.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
 // AVX: For now we support only conversion from Int/Long -> float
 // AVX512: Supports following conversions
 // srcType = float/double castToType = ulong
 // srcType = ulong castToType = double

 switch (from)
 {
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return ins_Move_Extend(TYP_FLOAT, false);
 case TYP_DOUBLE:
 return INS_cvtss2sd;
 case TYP_ULONG:
 return INS_vcvttss2usi64;
 default:
 unreached();
 }
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return INS_cvttsd2si;
 case TYP_LONG:
 return INS_cvttsd2si;
 case TYP_ULONG:
 return INS_vcvttsd2usi;
 case TYP_FLOAT:
 return INS_cvtsd2ss;
 case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 }
 break;

 case TYP_ULONG:
 switch (to)
 {
 case TYP_DOUBLE:
 return INS_vcvtusi2sd64;
 default:
 unreached();
 }

 default:
 unreached();
 }
Expand Down

3 changes: 2 additions & 1 deletion
src/coreclr/jit/instrsxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/lowerxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
 // srcType = float/double castToType = * and overflow detecting cast
 // Reason: must be converted to a helper call
 // srcType = float/double, castToType = ulong
 // Reason: must be converted to a helper call
 // Reason: must be converted to a helper call unless we have AVX512F
 // srcType = uint castToType = float/double
 // Reason: uint -> float/double = uint -> long -> float/double
 // srcType = ulong castToType = float
 // Reason: ulong -> float = ulong -> double -> float
 if (varTypeIsFloating(srcType))
 if (srcType == TYP_FLOAT)
 {
 noway_assert(!tree->gtOverflow());
 noway_assert(castToType != TYP_ULONG);
 noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 }
 else if (srcType == TYP_UINT)
 {
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/jit/morph.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

 case TYP_ULONG:
#ifdef TARGET_AMD64
 if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 return nullptr;
#endif
 return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
 default:
 unreached();
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default");
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and
privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Closed

khushal1996
wants to merge
13
commits into

from

 Closed


Isolating JITDbl2Ulng helper changes
#86175
Show file tree
Hide file tree
 Changes from all commits
Commits

Show all changes


13 commits


Select commit
Hold shift + click to select a range
7bae37a

fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…


khushal1996 May 9, 2023
73dc4c4

Making changes to the library test case expected output based on the …


khushal1996 May 10, 2023
fbc134d

Fixing the JITDbl2Ulng helper function. Also making sure that we are …


khushal1996 May 12, 2023
293e84d

reverting jitformat


khushal1996 May 12, 2023
6d14c22

Adding a truncate function to the Dbl2Ulng helper to make sure we avo…


khushal1996 May 15, 2023
d977447

Adding code to handle vectorized conversion for float/double to/from …


khushal1996 May 16, 2023
0845905

reverting changes for float to ulong


khushal1996 May 16, 2023
451780e

enabling float to ulong conversion


khushal1996 May 16, 2023
06ecf6a

Making change to set w1 bit for evex


khushal1996 May 17, 2023
6b963e6

trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…


khushal1996 May 18, 2023
e8f06d9

jit format


khushal1996 May 18, 2023
c703c1b

Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…


khushal1996 May 18, 2023
bb4a91e

undoing jitformat changes due to merge error


khushal1996 May 18, 2023

File filter

Filter by extension
Filter by extension
Conversations

Failed to load comments. 
Loading
Jump to

Jump to file


Failed to load files. 
Loading
 Diff view

 Diff view


20 changes: 17 additions & 3 deletions
src/coreclr/jit/codegenxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
 noway_assert(srcType != TYP_UINT);
 noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

 if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 {
 if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
 {
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
 genProduceReg(treeNode);
 return;
 }
 }

 // To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
 // which does a partial write to lower 4/8 bytes of xmm register keeping the other
 // upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

 // We shouldn't be seeing uint64 here as it should have been converted
 // into a helper call by either front-end or lowering phase.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
 // into a helper call by either front-end or lowering phase, unless we have AVX512F
 // accelerated conversions.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
 compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

 // If the dstType is TYP_UINT, we have 32-bits to encode the
 // float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 // Note that we need to specify dstType here so that it will determine
 // the size of destination integer register and also the rex.w prefix.
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
 genProduceReg(treeNode);
}
Expand Down

9 changes: 9 additions & 0 deletions
src/coreclr/jit/emit.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
 return EA_32BYTE;
 }

 case INS_vcvttss2usi64:
 {
 if (defaultSize == 8)
 {
 return EA_4BYTE;
 }
 return defaultSize;
 }

 case INS_movddup:
 {
 if (defaultSize == 64)
Expand Down

35 changes: 29 additions & 6 deletions
src/coreclr/jit/emitxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 if (attr == EA_8BYTE)
 {
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 // These SSE instructions write to a general purpose integer register.
 return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
 break;
 }

 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
 break;
 }

#ifdef TARGET_AMD64
 case INS_movsxd:
 {
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
 case INS_cvtsi2sd64:
 case INS_cvtsi2ss64:
 case INS_vcvtsd2usi:
 case INS_vcvttsd2usi:
 case INS_vcvtusi2sd32:
 case INS_vcvtusi2sd64:
 case INS_vcvtusi2ss32:
 case INS_vcvtusi2ss64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttsd2usi:
 result.insLatency += PERFSCORE_LATENCY_6C;
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 break;

 case INS_vcvtusi2sd64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
 break;

 case INS_cvttss2si:
 case INS_cvtss2si:
 case INS_vcvtss2usi:
 case INS_vcvttss2usi:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi32:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_8C;
 break;

 case INS_cvtss2sd:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/hwintrinsiclistxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down

16 changes: 16 additions & 0 deletions
src/coreclr/jit/instr.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
 // AVX: For now we support only conversion from Int/Long -> float
 // AVX512: Supports following conversions
 // srcType = float/double castToType = ulong
 // srcType = ulong castToType = double

 switch (from)
 {
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return ins_Move_Extend(TYP_FLOAT, false);
 case TYP_DOUBLE:
 return INS_cvtss2sd;
 case TYP_ULONG:
 return INS_vcvttss2usi64;
 default:
 unreached();
 }
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return INS_cvttsd2si;
 case TYP_LONG:
 return INS_cvttsd2si;
 case TYP_ULONG:
 return INS_vcvttsd2usi;
 case TYP_FLOAT:
 return INS_cvtsd2ss;
 case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 }
 break;

 case TYP_ULONG:
 switch (to)
 {
 case TYP_DOUBLE:
 return INS_vcvtusi2sd64;
 default:
 unreached();
 }

 default:
 unreached();
 }
Expand Down

3 changes: 2 additions & 1 deletion
src/coreclr/jit/instrsxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/lowerxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
 // srcType = float/double castToType = * and overflow detecting cast
 // Reason: must be converted to a helper call
 // srcType = float/double, castToType = ulong
 // Reason: must be converted to a helper call
 // Reason: must be converted to a helper call unless we have AVX512F
 // srcType = uint castToType = float/double
 // Reason: uint -> float/double = uint -> long -> float/double
 // srcType = ulong castToType = float
 // Reason: ulong -> float = ulong -> double -> float
 if (varTypeIsFloating(srcType))
 if (srcType == TYP_FLOAT)
 {
 noway_assert(!tree->gtOverflow());
 noway_assert(castToType != TYP_ULONG);
 noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 }
 else if (srcType == TYP_UINT)
 {
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/jit/morph.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

 case TYP_ULONG:
#ifdef TARGET_AMD64
 if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 return nullptr;
#endif
 return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
 default:
 unreached();
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Remove or un-stick sticky/fixed headers that block content\n(function() {\n function unstick() {\n document.querySelectorAll('header, nav, [role=\"banner\"], .header, .navbar, .sticky, .fixed-top, [style*=\"position: fixed\"], [style*=\"position:sticky\"]').forEach(function(el) {\n if (el.style.position === 'fixed' || el.style.position === 'sticky' || \n getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {\n el.style.position = 'static';\n el.style.top = 'auto';\n el.style.zIndex = 'auto';\n }\n });\n }\n \n unstick();\n \n var observer = new MutationObserver(unstick);\n observer.observe(document.body, { childList: true, subtree: true, attributes: true, attributeFilter: ['style', 'class'] });\n})();", "Kill Sticky Headers");
}
} catch(__e) { console.warn('[Userscript:Kill Sticky Headers]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and
privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Closed

khushal1996
wants to merge
13
commits into

from

 Closed


Isolating JITDbl2Ulng helper changes
#86175
Show file tree
Hide file tree
 Changes from all commits
Commits

Show all changes


13 commits


Select commit
Hold shift + click to select a range
7bae37a

fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…


khushal1996 May 9, 2023
73dc4c4

Making changes to the library test case expected output based on the …


khushal1996 May 10, 2023
fbc134d

Fixing the JITDbl2Ulng helper function. Also making sure that we are …


khushal1996 May 12, 2023
293e84d

reverting jitformat


khushal1996 May 12, 2023
6d14c22

Adding a truncate function to the Dbl2Ulng helper to make sure we avo…


khushal1996 May 15, 2023
d977447

Adding code to handle vectorized conversion for float/double to/from …


khushal1996 May 16, 2023
0845905

reverting changes for float to ulong


khushal1996 May 16, 2023
451780e

enabling float to ulong conversion


khushal1996 May 16, 2023
06ecf6a

Making change to set w1 bit for evex


khushal1996 May 17, 2023
6b963e6

trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…


khushal1996 May 18, 2023
e8f06d9

jit format


khushal1996 May 18, 2023
c703c1b

Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…


khushal1996 May 18, 2023
bb4a91e

undoing jitformat changes due to merge error


khushal1996 May 18, 2023

File filter

Filter by extension
Filter by extension
Conversations

Failed to load comments. 
Loading
Jump to

Jump to file


Failed to load files. 
Loading
 Diff view

 Diff view


20 changes: 17 additions & 3 deletions
src/coreclr/jit/codegenxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
 noway_assert(srcType != TYP_UINT);
 noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

 if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 {
 if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
 {
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
 genProduceReg(treeNode);
 return;
 }
 }

 // To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
 // which does a partial write to lower 4/8 bytes of xmm register keeping the other
 // upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

 // We shouldn't be seeing uint64 here as it should have been converted
 // into a helper call by either front-end or lowering phase.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
 // into a helper call by either front-end or lowering phase, unless we have AVX512F
 // accelerated conversions.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
 compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

 // If the dstType is TYP_UINT, we have 32-bits to encode the
 // float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 // Note that we need to specify dstType here so that it will determine
 // the size of destination integer register and also the rex.w prefix.
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
 genProduceReg(treeNode);
}
Expand Down

9 changes: 9 additions & 0 deletions
src/coreclr/jit/emit.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
 return EA_32BYTE;
 }

 case INS_vcvttss2usi64:
 {
 if (defaultSize == 8)
 {
 return EA_4BYTE;
 }
 return defaultSize;
 }

 case INS_movddup:
 {
 if (defaultSize == 64)
Expand Down

35 changes: 29 additions & 6 deletions
src/coreclr/jit/emitxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 if (attr == EA_8BYTE)
 {
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 // These SSE instructions write to a general purpose integer register.
 return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
 break;
 }

 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
 break;
 }

#ifdef TARGET_AMD64
 case INS_movsxd:
 {
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
 case INS_cvtsi2sd64:
 case INS_cvtsi2ss64:
 case INS_vcvtsd2usi:
 case INS_vcvttsd2usi:
 case INS_vcvtusi2sd32:
 case INS_vcvtusi2sd64:
 case INS_vcvtusi2ss32:
 case INS_vcvtusi2ss64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttsd2usi:
 result.insLatency += PERFSCORE_LATENCY_6C;
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 break;

 case INS_vcvtusi2sd64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
 break;

 case INS_cvttss2si:
 case INS_cvtss2si:
 case INS_vcvtss2usi:
 case INS_vcvttss2usi:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi32:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_8C;
 break;

 case INS_cvtss2sd:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/hwintrinsiclistxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down

16 changes: 16 additions & 0 deletions
src/coreclr/jit/instr.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
 // AVX: For now we support only conversion from Int/Long -> float
 // AVX512: Supports following conversions
 // srcType = float/double castToType = ulong
 // srcType = ulong castToType = double

 switch (from)
 {
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return ins_Move_Extend(TYP_FLOAT, false);
 case TYP_DOUBLE:
 return INS_cvtss2sd;
 case TYP_ULONG:
 return INS_vcvttss2usi64;
 default:
 unreached();
 }
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return INS_cvttsd2si;
 case TYP_LONG:
 return INS_cvttsd2si;
 case TYP_ULONG:
 return INS_vcvttsd2usi;
 case TYP_FLOAT:
 return INS_cvtsd2ss;
 case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 }
 break;

 case TYP_ULONG:
 switch (to)
 {
 case TYP_DOUBLE:
 return INS_vcvtusi2sd64;
 default:
 unreached();
 }

 default:
 unreached();
 }
Expand Down

3 changes: 2 additions & 1 deletion
src/coreclr/jit/instrsxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/lowerxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
 // srcType = float/double castToType = * and overflow detecting cast
 // Reason: must be converted to a helper call
 // srcType = float/double, castToType = ulong
 // Reason: must be converted to a helper call
 // Reason: must be converted to a helper call unless we have AVX512F
 // srcType = uint castToType = float/double
 // Reason: uint -> float/double = uint -> long -> float/double
 // srcType = ulong castToType = float
 // Reason: ulong -> float = ulong -> double -> float
 if (varTypeIsFloating(srcType))
 if (srcType == TYP_FLOAT)
 {
 noway_assert(!tree->gtOverflow());
 noway_assert(castToType != TYP_ULONG);
 noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 }
 else if (srcType == TYP_UINT)
 {
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/jit/morph.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

 case TYP_ULONG:
#ifdef TARGET_AMD64
 if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 return nullptr;
#endif
 return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
 default:
 unreached();
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Universal Dark Mode - works on any site\n(function() {\n var enabled = true;\n \n function applyDarkMode() {\n if (!enabled) return;\n \n // Create style element if it doesn't exist\n var style = document.getElementById('universal-dark-mode-style');\n if (!style) {\n style = document.createElement('style');\n style.id = 'universal-dark-mode-style';\n document.head.appendChild(style);\n }\n \n // Dark mode CSS - inverts colors but preserves images/video\n style.textContent = '\n /* Invert everything except media */\n html {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #1a1a2e !important;\n }\n \n /* Restore images, videos, iframes, canvas */\n img, video, iframe, canvas, svg, picture, [style*=\"background-image\"] {\n filter: invert(1) hue-rotate(180deg) !important;\n }\n \n /* Preserve specific elements that should not be inverted */\n .no-dark-mode, .no-dark-mode *,\n [data-theme=\"light\"], [data-theme=\"light\"],\n .ace_editor, .ace_editor *,\n .CodeMirror, .CodeMirror *,\n .monaco-editor, .monaco-editor *,\n .markdown-body pre, .markdown-body pre *,\n .highlight, .highlight *,\n pre code, pre code * {\n filter: none !important;\n }\n \n /* Fix common UI elements */\n .modal, .popup, .dropdown-menu, .tooltip, .popover {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #2d2d44 !important;\n border-color: #444 !important;\n }\n \n /* Scrollbars */\n ::-webkit-scrollbar { background: #1a1a2e !important; }\n ::-webkit-scrollbar-thumb { background: #444 !important; }\n ::-webkit-scrollbar-thumb:hover { background: #555 !important; }\n \n /* Selection */\n ::selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ::-moz-selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ';\n }\n \n function removeDarkMode() {\n var style = document.getElementById('universal-dark-mode-style');\n if (style) style.remove();\n }\n \n // Toggle with Alt+Shift+D\n document.addEventListener('keydown', function(e) {\n if (e.altKey && e.shiftKey && e.key === 'D') {\n e.preventDefault();\n enabled = !enabled;\n if (enabled) {\n applyDarkMode();\n console.log('[Universal Dark Mode] Enabled');\n } else {\n removeDarkMode();\n console.log('[Universal Dark Mode] Disabled');\n }\n }\n });\n \n // Apply on load\n applyDarkMode();\n \n // Re-apply on dynamic content\n var observer = new MutationObserver(function(mutations) {\n if (enabled && !document.getElementById('universal-dark-mode-style')) {\n applyDarkMode();\n }\n });\n observer.observe(document.head, { childList: true });\n \n console.log('[Universal Dark Mode] Loaded - Press Alt+Shift+D to toggle');\n})();", "Universal Dark Mode");
}
} catch(__e) { console.warn('[Userscript:Universal Dark Mode]', __e); }
})();
})();

Skip to content
Isolating JITDbl2Ulng helper changes#86175

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and
privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Closed

khushal1996
wants to merge
13
commits into

from

 Closed


Isolating JITDbl2Ulng helper changes
#86175
Show file tree
Hide file tree
 Changes from all commits
Commits

Show all changes


13 commits


Select commit
Hold shift + click to select a range
7bae37a

fixing the JITDbl2Ulng helper function. The new AVX512 instruction vc…


khushal1996 May 9, 2023
73dc4c4

Making changes to the library test case expected output based on the …


khushal1996 May 10, 2023
fbc134d

Fixing the JITDbl2Ulng helper function. Also making sure that we are …


khushal1996 May 12, 2023
293e84d

reverting jitformat


khushal1996 May 12, 2023
6d14c22

Adding a truncate function to the Dbl2Ulng helper to make sure we avo…


khushal1996 May 15, 2023
d977447

Adding code to handle vectorized conversion for float/double to/from …


khushal1996 May 16, 2023
0845905

reverting changes for float to ulong


khushal1996 May 16, 2023
451780e

enabling float to ulong conversion


khushal1996 May 16, 2023
06ecf6a

Making change to set w1 bit for evex


khushal1996 May 17, 2023
6b963e6

trying to return EA_4BYTE for INS_vcvttss2usi to make sure that we re…


khushal1996 May 18, 2023
e8f06d9

jit format


khushal1996 May 18, 2023
c703c1b

Splitting vcvttss2usi to vcvttss2usi32 and vcvttss2usi64. Also adding…


khushal1996 May 18, 2023
bb4a91e

undoing jitformat changes due to merge error


khushal1996 May 18, 2023

File filter

Filter by extension
Filter by extension
Conversations

Failed to load comments. 
Loading
Jump to

Jump to file


Failed to load files. 
Loading
 Diff view

 Diff view


20 changes: 17 additions & 3 deletions
src/coreclr/jit/codegenxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -7451,6 +7451,18 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)
 noway_assert(srcType != TYP_UINT);
 noway_assert((srcType != TYP_ULONG) || (dstType != TYP_FLOAT));

 if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 {
 if (srcType == TYP_ULONG && (dstType == TYP_DOUBLE || dstType == TYP_FLOAT))
 {
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);
 genProduceReg(treeNode);
 return;
 }
 }

 // To convert int to a float/double, cvtsi2ss/sd SSE2 instruction is used
 // which does a partial write to lower 4/8 bytes of xmm register keeping the other
 // upper bytes unmodified. If "cvtsi2ss/sd xmmReg, r32/r64" occurs inside a loop,
Expand DownExpand Up@@ -7562,8 +7574,10 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 noway_assert((dstSize == EA_ATTR(genTypeSize(TYP_INT))) || (dstSize == EA_ATTR(genTypeSize(TYP_LONG))));

 // We shouldn't be seeing uint64 here as it should have been converted
 // into a helper call by either front-end or lowering phase.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))));
 // into a helper call by either front-end or lowering phase, unless we have AVX512F
 // accelerated conversions.
 noway_assert(!varTypeIsUnsigned(dstType) || (dstSize != EA_ATTR(genTypeSize(TYP_LONG))) ||
 compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F));

 // If the dstType is TYP_UINT, we have 32-bits to encode the
 // float number. Any of 33rd or above bits can be the sign bit.
Expand All@@ -7576,7 +7590,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
 // Note that we need to specify dstType here so that it will determine
 // the size of destination integer register and also the rex.w prefix.
 genConsumeOperands(treeNode->AsOp());
 instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
 instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(srcType));
 GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
 genProduceReg(treeNode);
}
Expand Down

9 changes: 9 additions & 0 deletions
src/coreclr/jit/emit.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3857,6 +3857,15 @@ emitAttr emitter::emitGetMemOpSize(instrDesc* id) const
 return EA_32BYTE;
 }

 case INS_vcvttss2usi64:
 {
 if (defaultSize == 8)
 {
 return EA_4BYTE;
 }
 return defaultSize;
 }

 case INS_movddup:
 {
 if (defaultSize == 64)
Expand Down

35 changes: 29 additions & 6 deletions
src/coreclr/jit/emitxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -1294,7 +1294,6 @@ bool emitter::TakesRexWPrefix(const instrDesc* id) const
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 if (attr == EA_8BYTE)
 {
Expand DownExpand Up@@ -2518,7 +2517,8 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 // These SSE instructions write to a general purpose integer register.
 return false;
Expand DownExpand Up@@ -11234,12 +11234,18 @@ void emitter::emitDispIns(
 case INS_vcvtsd2usi:
 case INS_vcvtss2usi:
 case INS_vcvttsd2usi:
 case INS_vcvttss2usi:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_16BYTE));
 break;
 }

 case INS_vcvttss2usi32:
 case INS_vcvttss2usi64:
 {
 printf(" %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), EA_4BYTE));
 break;
 }

#ifdef TARGET_AMD64
 case INS_movsxd:
 {
Expand DownExpand Up@@ -18157,23 +18163,40 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
 case INS_cvtsi2sd64:
 case INS_cvtsi2ss64:
 case INS_vcvtsd2usi:
 case INS_vcvttsd2usi:
 case INS_vcvtusi2sd32:
 case INS_vcvtusi2sd64:
 case INS_vcvtusi2ss32:
 case INS_vcvtusi2ss64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttsd2usi:
 result.insLatency += PERFSCORE_LATENCY_6C;
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 break;

 case INS_vcvtusi2sd64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
 break;

 case INS_cvttss2si:
 case INS_cvtss2si:
 case INS_vcvtss2usi:
 case INS_vcvttss2usi:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += opSize == EA_8BYTE ? PERFSCORE_LATENCY_8C : PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi32:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_7C;
 break;

 case INS_vcvttss2usi64:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_8C;
 break;

 case INS_cvtss2sd:
 result.insThroughput = PERFSCORE_THROUGHPUT_1C;
 result.insLatency += PERFSCORE_LATENCY_5C;
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/hwintrinsiclistxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -836,7 +836,7 @@ HARDWARE_INTRINSIC(AVX512F, Ceiling,
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss32, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToUInt32WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi32, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Byte, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovdb, INS_vpmovdb, INS_vpmovqb, INS_vpmovqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128ByteWithSaturation, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovusdb, INS_invalid, INS_vpmovusqb, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F, ConvertToVector128Int16, 64, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vpmovqw, INS_vpmovqw, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
Expand DownExpand Up@@ -948,7 +948,7 @@ HARDWARE_INTRINSIC(AVX512F_VL, ShiftRightArithmeticVariable,
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Double, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2sd64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertScalarToVector128Single, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtusi2ss64, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_CopyUpperBits|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvtss2usi, INS_vcvtsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi,  INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AVX512F_X64, ConvertToUInt64WithTruncation, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_vcvttss2usi64, INS_vcvttsd2usi}, HW_Category_SIMDScalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name SIMD size NumArg Instructions Category Flags
Expand Down

16 changes: 16 additions & 0 deletions
src/coreclr/jit/instr.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2165,6 +2165,9 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type)
instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
{
 // AVX: For now we support only conversion from Int/Long -> float
 // AVX512: Supports following conversions
 // srcType = float/double castToType = ulong
 // srcType = ulong castToType = double

 switch (from)
 {
Expand DownExpand Up@@ -2213,6 +2216,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return ins_Move_Extend(TYP_FLOAT, false);
 case TYP_DOUBLE:
 return INS_cvtss2sd;
 case TYP_ULONG:
 return INS_vcvttss2usi64;
 default:
 unreached();
 }
Expand All@@ -2225,6 +2230,8 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 return INS_cvttsd2si;
 case TYP_LONG:
 return INS_cvttsd2si;
 case TYP_ULONG:
 return INS_vcvttsd2usi;
 case TYP_FLOAT:
 return INS_cvtsd2ss;
 case TYP_DOUBLE:
Expand All@@ -2234,6 +2241,15 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from, emitAttr attr)
 }
 break;

 case TYP_ULONG:
 switch (to)
 {
 case TYP_DOUBLE:
 return INS_vcvtusi2sd64;
 default:
 unreached();
 }

 default:
 unreached();
 }
Expand Down

3 changes: 2 additions & 1 deletion
src/coreclr/jit/instrsxarch.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -626,7 +626,8 @@ INST3(vcvtss2usi, "cvtss2usi", IUM_WR, BAD_CODE, BAD_
INST3(vcvttpd2udq, "cvttpd2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_64Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation packed doubles to unsigned DWORDs
INST3(vcvttps2udq, "cvttps2udq", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x78), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation packed singles to unsigned DWORDs
INST3(vcvttsd2usi, "cvttsd2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x78), INS_TT_TUPLE1_FIXED, Input_64Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar double to unsigned DWORD/QWORD
INST3(vcvttss2usi, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_WX | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi32, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvttss2usi64, "cvttss2usi", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x78), INS_TT_TUPLE1_FIXED, Input_32Bit | REX_W1 | Encoding_EVEX) // cvt w/ truncation scalar single to unsigned DWORD/QWORD
INST3(vcvtudq2pd, "cvtudq2pd", IUM_WR, BAD_CODE, BAD_CODE, SSEFLT(0x7A), INS_TT_HALF, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to doubles
INST3(vcvtudq2ps, "cvtudq2ps", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7A), INS_TT_FULL, Input_32Bit | REX_W0 | Encoding_EVEX) // cvt packed unsigned DWORDs to singles
INST3(vcvtusi2sd32, "cvtusi2sd", IUM_WR, BAD_CODE, BAD_CODE, SSEDBL(0x7B), INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // cvt scalar unsigned DWORD to double
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/lowerxarch.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -795,15 +795,15 @@ void Lowering::LowerCast(GenTree* tree)
 // srcType = float/double castToType = * and overflow detecting cast
 // Reason: must be converted to a helper call
 // srcType = float/double, castToType = ulong
 // Reason: must be converted to a helper call
 // Reason: must be converted to a helper call unless we have AVX512F
 // srcType = uint castToType = float/double
 // Reason: uint -> float/double = uint -> long -> float/double
 // srcType = ulong castToType = float
 // Reason: ulong -> float = ulong -> double -> float
 if (varTypeIsFloating(srcType))
 if (srcType == TYP_FLOAT)
 {
 noway_assert(!tree->gtOverflow());
 noway_assert(castToType != TYP_ULONG);
 noway_assert(!tree->gtOverflow() || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 noway_assert(castToType != TYP_ULONG || comp->compOpportunisticallyDependsOn(InstructionSet_AVX512F));
 }
 else if (srcType == TYP_UINT)
 {
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/jit/morph.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -358,6 +358,10 @@ GenTree* Compiler::fgMorphExpandCast(GenTreeCast* tree)
#endif // !TARGET_AMD64

 case TYP_ULONG:
#ifdef TARGET_AMD64
 if (compOpportunisticallyDependsOn(InstructionSet_AVX512F))
 return nullptr;
#endif
 return fgMorphCastIntoHelper(tree, CORINFO_HELP_DBL2ULNG, oper);
 default:
 unreached();
Expand Down
Loading