JIT: experimental changes to redundant branch opts

[AndyAyersMS]

Recognize a particular case where a control flow pattern involving two BBJ_COND blocks with relops that test the same VNs can be simplified to a single relop in the dominating block.

As part of this, teach VN about some of the rudiments of boolean simplification (DeMorgan's laws) and how to simplify some NOT / AND / OR expressions involving relops.

Addresses some of the cases in #81220.

[This is an updated version of #83859]

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Issue Details

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Recognize a particular case where a control flow pattern involving two BBJ_COND blocks with relops that test the same VNs can be simplified to a single relop in the dominating block.

As part of this, teach VN about some of the rudiments of boolean simplification (DeMorgan's laws) and how to simplify some NOT / AND / OR expressions involving relops.

Addresses some of the cases in #81220.

[This is an updated version of #83859]

Author:	AndyAyersMS
Assignees:	-
Labels:	area-CodeGen-coreclr
Milestone:	-

[hez2010]

Will this also fix #88025 (comment)?

[AndyAyersMS]

Failure looks similar to #88579 (timeout in remote executor)

[AndyAyersMS]

Will this also fix #88025 (comment)?

No, it doesn't fix that case (though it does a ton of flow graph simplification). Seems like for that we could try running a late tail merge...? That should be fairly cheap, let me see what happens.

[AndyAyersMS]

Will this also fix #88025 (comment)?

No, it doesn't fix that case (though it does a ton of flow graph simplification). Seems like for that we could try running a late tail merge...? That should be fairly cheap, let me see what happens.

Well, not quite that simple, we are left with this sort of thing after running opts and fg cleanup:

***** BB22
STMT00082 ( INL22 @ 0x009[E-] ... ??? ) <- INL21 @ 0x010[E-] <- INL04 @ 0x030[E-] <- INL03 @ 0x000[E-] <- INLRT @ 0x020[--]
N002 ( 5, 4) [000334] DA--------- * STORE_LCL_VAR int V24 tmp24 d:3 $VN.Void
N001 ( 1, 1) [000333] ----------- \--* CNS_INT int 0 $41
***** BB22
STMT00073 ( INL21 @ 0x010[E-] ... ??? ) <- INL04 @ 0x030[E-] <- INL03 @ 0x000[E-] <- INLRT @ 0x020[--]
N002 ( 8, 6) [000304] DA--------- * STORE_LCL_VAR int V21 tmp21 d:4 $VN.Void
N001 ( 4, 3) [000339] ----------- \--* LCL_VAR bool V24 tmp24 u:1 (last use) $301
***** BB22
STMT00023 ( INL04 @ 0x030[E-] ... ??? ) <- INL03 @ 0x000[E-] <- INLRT @ 0x020[--]
N002 ( 8, 6) [000094] DA--------- * STORE_LCL_VAR int V06 tmp6 d:3 $VN.Void
N001 ( 4, 3) [000305] ----------- \--* LCL_VAR bool V21 tmp21 u:1 (last use) $302
------------ BB41 [020..021), preds={BB01} succs={BB42}
***** BB41
STMT00017 ( INL04 @ 0x047[E-] ... ??? ) <- INL03 @ 0x000[E-] <- INLRT @ 0x020[--]
N002 ( 5, 4) [000065] DA--------- * STORE_LCL_VAR int V06 tmp6 d:2 $VN.Void
N001 ( 1, 1) [000064] ----------- \--* CNS_INT int 0 $41
------------ BB42 [020..026) (return), preds={BB22,BB41} succs={}
***** BB42
STMT00106 ( ??? ... ??? )
N004 ( 0, 0) [000496] DA--------- * STORE_LCL_VAR bool V06 tmp6 d:1 $VN.Void
N003 ( 0, 0) [000495] ----------- \--* PHI bool $303
N001 ( 0, 0) [000504] ----------- pred BB40 +--* PHI_ARG bool V06 tmp6 u:3 $343
N002 ( 0, 0) [000503] ----------- pred BB41 \--* PHI_ARG bool V06 tmp6 u:2 $41
***** BB42
STMT00004 ( 0x020[--] ... ??? )
N002 ( 5, 4) [000016] ----------- * RETURN int $VN.Void
N001 ( 4, 3) [000095] ----------- \--* LCL_VAR bool V06 tmp6 u:1 (last use) $303

As you can see this should all collapse to returning zero, but tail merging is hindered by the no-longer relevant PHI and the fact that the zero in BB22 needs to propagate through a few intermediate assignments.

You might wonder why we didn't realize that V06 was zero in BB22 sooner, it comes down to the fact that as RBO removes branches we're not able to take maximum advantage by updating VNs to reflect the more refined flow.

A more heavy-weight optimizer might rebuild SSA/VN after RBO, or run multiple passes of optimization, but that's not something we would do lightly...

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