[RISC-V] Fix GitHub_* tests

[clamp03]

• Fix an assertion in GitHub_17585 by updating DISPATCH STUB
• Fix a invalid result in GitHub_23147 by updating genJmpMethod in codegenriscv64.cpp

FAILED - [ 20s]./JIT/Regression/JitBlue/GitHub_17585/GitHub_17585/GitHub_17585.sh
BEGIN EXECUTION
/work/dotnet/riscv64/artifacts/tests/coreclr/linux.riscv64.Checked/Tests/Core_Root/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false -p System.Runtime.Serialization.EnableUnsafeBinaryFormatterSerialization=true GitHub_17585.dll ''
Assert failure(PID 637342 [0x0009b99e], Thread: 637342 [0x9b99e]): !"AV in DispatchStub at unknown instruction"
File: /home/clamp/Work/dotnet/riscv64/src/coreclr/vm/riscv64/stubs.cpp Line: 876
Image: /work/dotnet/riscv64/artifacts/tests/coreclr/linux.riscv64.Checked/Tests/Core_Root/corerun
./GitHub_17585.sh: line 448: 637342 Aborted (core dumped) $LAUNCHER $ExePath "${CLRTestExecutionArguments[@]}"
Expected: 100
Actual: 134
END EXECUTION - FAILED
FAILED - [ 14s]./JIT/Regression/JitBlue/GitHub_23147/GitHub_23147/GitHub_23147.sh
BEGIN EXECUTION
/work/dotnet/jobs/riscv/bugfix/artifacts/tests/coreclr/linux.riscv64.Checked/Tests/Core_Root/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false -p System.Runtime.Serialization.EnableUnsafeBinaryFormatterSerialization=true GitHub_23147.dll ''
jmp_test_f2 FAIL
jmp_test_f3 PASS
jmp_test_f4 PASS
jmp_test_d2 PASS
jmp_test_d3 PASS
jmp_test_d4 PASS
Expected: 100
Actual: 1
END EXECUTION - FAILED

Part of #84834
cc @wscho77@HJLeee@JongHeonChoi@t-mustafin@alpencolt@gbalykov

[alpencolt]

HFA is ARM only concept. I think this assert isn't needed.

[clamp03]

Removed. Thank you.

[alpencolt]

It's code from LA64, when I made genJmpMethod() implementation, I've took ARM64 version since it's more clear. E.g. what's the meaning of if (varDsc->GetOtherArgReg() < REG_STK)?

[clamp03]

Because ARM64 and RISCV have different calling convention. Right, ARM64 seems more clearer, but RISCV follows LA64's. So we need to update like LA64.
GetOtherArgReg is the second register for multi argument register for RISCV and LA64.

In case of ARM64 in the test, it passes two float register arguments using one int register (REG_A0). So compiler->lvaIsMultiregStruct returns false. In method prolog in a callee, it makes two float values from REG_A0 in ARM64.

[alpencolt]

And why special case for float is need?

[clamp03]

Because it cannot get the exact type by using varDsc->GetLayout()->GetGCPtrType(1) (only returns TYP_I_IMPL for all primitive and non-gc value type) and GetEmitter()->emitIns_R_S needs the exact type for the arguments.

If you want to update calling convention like ARM64, we can do. However, I think it is better to investigate after RISC-V is stable.

[clamp03]

@jkotas@jakobbotsch Could you please review? Thank you so much.

[jkotas]

The virtualcallstubcpu.hpp change looks good.

@jakobbotsch Could you please review the JIT change?