Arm64/SVE: Add Uzp1

src/coreclr/jit/codegenarm64.cpp

@@ -6702,6 +6702,14 @@ void CodeGen::genArm64EmitterUnitTests()
  theEmitter->emitIns_R_R_R(INS_asrv, EA_4BYTE, REG_R8, REG_R9, REG_R10);
  theEmitter->emitIns_R_R_R(INS_rorv, EA_4BYTE, REG_R8, REG_R9, REG_R10);
 
+ // TODO-SVE: Fix once we add predicate registers
+ theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2,
+ INS_OPTS_8B); // UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+ theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2,
+ INS_OPTS_8B); // UZP1 <Zd>.Q, <Zn>.Q, <Zm>.Q
+ theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2,
+ INS_OPTS_8B); // UZP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
+
 #endif // ALL_ARM64_EMITTER_UNIT_TESTS
 
 #ifdef ALL_ARM64_EMITTER_UNIT_TESTS

src/coreclr/jit/emitarm64.cpp

@@ -943,6 +943,31 @@ void emitter::emitInsSanityCheck(instrDesc* id)
  assert(datasize == EA_8BYTE);
  break;
 
+ case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments
+ elemsize = id->idOpSize();
+ assert(insOptsNone(id->idInsOpt()));
+ assert(isVectorRegister(id->idReg1())); // ddddd
+ assert(isVectorRegister(id->idReg2())); // nnnnn
+ assert(isVectorRegister(id->idReg3())); // mmmmm
+ assert(isValidVectorElemsize(elemsize)); // xx
+ break;
+
+ case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments
+ assert(insOptsNone(id->idInsOpt()));
+ assert(isVectorRegister(id->idReg1())); // ddddd
+ assert(isVectorRegister(id->idReg2())); // nnnnn
+ assert(isVectorRegister(id->idReg3())); // mmmmm
+ break;
+
+ case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
+ elemsize = id->idOpSize();
+ assert(insOptsNone(id->idInsOpt()));
+ assert(isPredicateRegister(id->idReg1())); // DDDD
+ assert(isPredicateRegister(id->idReg2())); // NNNN
+ assert(isPredicateRegister(id->idReg3())); // MMMM
+ assert(isValidVectorElemsize(elemsize)); // xx
+ break;
+
  default:
  printf("unexpected format %s\n", emitIfName(id->idInsFmt()));
  assert(!"Unexpected format");
@@ -1021,6 +1046,10 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
  case IF_DV_3F: // DV_3F .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
  case IF_DV_3G: // DV_3G .Q.........mmmmm .iiii.nnnnnddddd Vd Vn Vm imm (vector)
  case IF_DV_4A: // DV_4A .........X.mmmmm .aaaaannnnnddddd Vd Va Vn Vm (scalar)
+
+ case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments
+ case IF_SVE_EF_3A: // ...........mmmmm ......nnnnnddddd -- SVE two-way dot product
+ case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
  // Tracked GC pointers cannot be placed into the SIMD registers.
  return false;
 
@@ -1420,6 +1449,25 @@ const char* emitter::emitVectorRegName(regNumber reg)
  return vRegNames[index];
 }
 
+//------------------------------------------------------------------------
+// emitPredicateRegName: Returns a predicate register name.
+//
+// Arguments:
+// reg - A predicate register.
+//
+// Return value:
+// A string that represents a predicate register name.
+//
+const char* emitter::emitPredicateRegName(regNumber reg)
+{
+ // TODO-SVE: Fix once we add predicate registers
+ assert((reg >= REG_V0) && (reg <= REG_V31));
+
+ int index = (int)reg - (int)REG_V0;
+
+ return vRegNames[index];
+}
+
 /*****************************************************************************
  *
  * Returns the base encoding of the given CPU instruction.
@@ -10571,6 +10619,47 @@ void emitter::emitIns_Call(EmitCallType callType,
  return ureg << 10;
 }
 
+/*****************************************************************************
+ *
+ * Returns an encoding for the specified register used in the 'Vd' position
+ */
+
+/*static*/ emitter::code_t emitter::insEncodeReg_Pd(regNumber reg)
+{
+ // TODO-SVE: Fix once we add predicate registers
+ assert(emitter::isPredicateRegister(reg));
+ emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
+ assert((ureg >= 0) && (ureg <= 15));
+ return ureg;
+}
+
+/*****************************************************************************
+ *
+ * Returns an encoding for the specified register used in the 'Vn' position
+ */
+
+/*static*/ emitter::code_t emitter::insEncodeReg_Pn(regNumber reg)
+{
+ // TODO-SVE: Fix once we add predicate registers
+ assert(emitter::isPredicateRegister(reg));
+ emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
+ assert((ureg >= 0) && (ureg <= 15));
+ return ureg << 5;
+}
+
+/*****************************************************************************
+ *
+ * Returns an encoding for the specified register used in the 'Vm' position
+ */
+
+/*static*/ emitter::code_t emitter::insEncodeReg_Pm(regNumber reg)
+{
+ // TODO-SVE: Fix once we add predicate registers
+ assert(emitter::isPredicateRegister(reg));
+ emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
+ assert((ureg >= 0) && (ureg <= 15));
+ return ureg << 16;
+}
 /*****************************************************************************
  *
  * Returns an encoding for the specified condition code.
@@ -13311,6 +13400,34 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
  dst += emitOutput_Instr(dst, code);
  break;
 
+ case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments
+ code = emitInsCodeSve(ins, fmt);
+ elemsize = id->idOpSize();
+ code |= insEncodeReg_Vd(id->idReg1()); // ddddd
+ code |= insEncodeReg_Vn(id->idReg2()); // nnnnn
+ code |= insEncodeReg_Vm(id->idReg3()); // mmmmm
+ code |= insEncodeElemsize(elemsize); // xx
+ dst += emitOutput_Instr(dst, code);
+ break;
+
+ case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments
+ code = emitInsCodeSve(ins, fmt);
+ code |= insEncodeReg_Vd(id->idReg1()); // ddddd
+ code |= insEncodeReg_Vn(id->idReg2()); // nnnnn
+ code |= insEncodeReg_Vm(id->idReg3()); // mmmmm
+ dst += emitOutput_Instr(dst, code);
+ break;
+
+ case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
+ code = emitInsCodeSve(ins, fmt);
+ elemsize = id->idOpSize();
+ code |= insEncodeReg_Pd(id->idReg1()); // DDDD
+ code |= insEncodeReg_Pn(id->idReg2()); // NNNN
+ code |= insEncodeReg_Pm(id->idReg3()); // MMMM
+ code |= insEncodeElemsize(elemsize); // xx
+ dst += emitOutput_Instr(dst, code);
+ break;
+
  default:
  assert(!"Unexpected format");
  break;
@@ -13849,6 +13966,20 @@ void emitter::emitDispVectorElemList(
  }
 }
 
+//------------------------------------------------------------------------
+// emitDispPredicateReg: Display a predicate register name with with an arrangement suffix
+//
+void emitter::emitDispPredicateReg(regNumber reg, insOpts opt, bool addComma)
+{
+ // TODO-SVE: Fix once we add predicate registers
+ assert(isPredicateRegister(reg));
+ printf(emitVectorRegName(reg));
+ emitDispArrangement(opt);
+
+ if (addComma)
+ emitDispComma();
+}
+
 //------------------------------------------------------------------------
 // emitDispArrangement: Display a SIMD vector arrangement suffix
 //
@@ -15444,6 +15575,24 @@ void emitter::emitDispInsHelp(
  }
  break;
 
+ case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments
+ emitDispVectorReg(id->idReg1(), id->idInsOpt(), true); // ddddd
+ emitDispVectorReg(id->idReg2(), id->idInsOpt(), true); // nnnnn
+ emitDispVectorReg(id->idReg3(), id->idInsOpt(), true); // mmmmm
+ break;
+
+ case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments
+ emitDispVectorReg(id->idReg1(), id->idInsOpt(), true); // ddddd
+ emitDispVectorReg(id->idReg2(), id->idInsOpt(), true); // nnnnn
+ emitDispVectorReg(id->idReg3(), id->idInsOpt(), true); // mmmmm
+ break;
+
+ case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
+ emitDispPredicateReg(id->idReg1(), id->idInsOpt(), true); // DDDD
+ emitDispPredicateReg(id->idReg2(), id->idInsOpt(), true); // NNNN
+ emitDispPredicateReg(id->idReg3(), id->idInsOpt(), true); // MMMM
+ break;
+
  default:
  printf("unexpected format %s", emitIfName(id->idInsFmt()));
  assert(!"unexpectedFormat");
@@ -17629,6 +17778,21 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
  }
  break;
 
+ case IF_SVE_BR_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments
+ result.insThroughput = PERFSCORE_THROUGHPUT_2X;
+ result.insLatency = PERFSCORE_LATENCY_2C;
+ break;
+
+ case IF_SVE_BR_3B: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector segments
+ result.insThroughput = PERFSCORE_THROUGHPUT_2X;
+ result.insLatency = PERFSCORE_LATENCY_2C;
+ break;
+
+ case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
+ result.insThroughput = PERFSCORE_THROUGHPUT_2X;
+ result.insLatency = PERFSCORE_LATENCY_2C;
+ break;
+
  default:
  // all other instructions
  perfScoreUnhandledInstruction(id, &result);

src/coreclr/jit/emitarm64.h

@@ -20,6 +20,7 @@ static bool strictArmAsm;
 /************************************************************************/
 
 const char* emitVectorRegName(regNumber reg);
+const char* emitPredicateRegName(regNumber reg);
 
 void emitDispInsHelp(
  instrDesc* id, bool isNew, bool doffs, bool asmfm, unsigned offset, BYTE* pCode, size_t sz, insGroup* ig);
@@ -42,6 +43,7 @@ void emitDispVectorReg(regNumber reg, insOpts opt, bool addComma);
 void emitDispVectorRegIndex(regNumber reg, emitAttr elemsize, ssize_t index, bool addComma);
 void emitDispVectorRegList(regNumber firstReg, unsigned listSize, insOpts opt, bool addComma);
 void emitDispVectorElemList(regNumber firstReg, unsigned listSize, emitAttr elemsize, unsigned index, bool addComma);
+void emitDispPredicateReg(regNumber reg, insOpts opt, bool addComma);
 void emitDispArrangement(insOpts opt);
 void emitDispElemsize(emitAttr elemsize);
 void emitDispShiftedReg(regNumber reg, insOpts opt, ssize_t imm, emitAttr attr);
@@ -312,6 +314,15 @@ static code_t insEncodeReg_Vm(regNumber reg);
 // Returns an encoding for the specified register used in the 'Va' position
 static code_t insEncodeReg_Va(regNumber reg);
 
+// Returns an encoding for the specified register used in the 'Pd' position
+static code_t insEncodeReg_Pd(regNumber reg);
+
+// Returns an encoding for the specified register used in the 'Pn' position
+static code_t insEncodeReg_Pn(regNumber reg);
+
+// Returns an encoding for the specified register used in the 'Pm' position
+static code_t insEncodeReg_Pm(regNumber reg);
+
 // Returns an encoding for the imm which represents the condition code.
 static code_t insEncodeCond(insCond cond);
 
@@ -664,6 +675,12 @@ inline static bool isFloatReg(regNumber reg)
  return isVectorRegister(reg);
 }
 
+inline static bool isPredicateRegister(regNumber reg)
+{
+ // TODO-SVE: Fix once we add predicate registers
+ return (reg >= REG_FP_FIRST && reg <= REG_FP_LAST);
+}
+
 inline static bool insOptsNone(insOpts opt)
 {
  return (opt == INS_OPTS_NONE);