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JIT: capture all write barrier helper addresses for SPMI - #97535
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When varying CSEs we can sometimes alter the write barrier that is needed. In particular if we CSE a heap address computation we may lose track of the fact that an indir is writing to the heap, and so change which write barrier needs to be used. See dotnet#97534. Even if that's fixed it seems like we still might change our minds for various reasons, so when running under SPMI, just collect all the possible write barrier helper addresses.
ghost
commented
Jan 26, 2024
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsWhen varying CSEs we can sometimes alter the write barrier that is needed. In particular if we CSE a heap address computation we may lose track of the fact that an indir is writing to the heap, and so change which write barrier needs to be used. See #97534. Even if that's fixed it seems like we still might change our minds for various reasons, so when running under SPMI, just collect all the possible write barrier helper addresses.
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AndyAyersMS
commented
Jan 26, 2024
@jakobbotsch PTAL |
| #ifdef DEBUG | ||
| bool genWriteBarrierUsed; | ||
| void WriteBarrierExtraSuperPmiQueries(); |
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Looks like you were going to use a function, but then you didn't?
Fixes an issue introduced by dotnet#97535. AOT hosts don't support all the possible write barriers and blow things up if the JIT asks for ones they don't support.
Fixes an issue introduced by #97535. AOT hosts don't support all the possible write barriers and blow things up if the JIT asks for ones they don't support. Also add back the initial semicolon to the metrics line
When varying CSEs we can sometimes alter the write barrier that is needed. In particular if we CSE a heap address computation we may lose track of the fact that an indir is writing to the heap, and so change which write barrier needs to be used.
See #97534.
Even if that's fixed it seems like we still might change our minds for various reasons, so when running under SPMI, just collect all the possible write barrier helper addresses.