Skip to content

[RISC-V] Remove unnecessary assertion from emitOutputInstr - #98484

Merged
jakobbotsch merged 3 commits into
dotnet:mainfrom
tomeksowi:fix-emitOutputInstr
Feb 19, 2024
Merged

[RISC-V] Remove unnecessary assertion from emitOutputInstr#98484
jakobbotsch merged 3 commits into
dotnet:mainfrom
tomeksowi:fix-emitOutputInstr

Conversation

@tomeksowi

@tomeksowitomeksowi commented Feb 15, 2024

Copy link
Copy Markdown
Member

Remove unnecessary assertion introduced in #98226. It fired a false positive when W^X was enabled.

Part of #84834
cc @wscho77@HJLeee@clamp03@JongHeonChoi@t-mustafin@gbalykov@viewizard@ashaurtaev@brucehoult@sirntar@yurai007@Bajtazar@bartlomiejko

It fired a false positive when W^X was enabled
@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Feb 15, 2024
@ghost

Copy link
Copy Markdown

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

Remove unnecessary assertion. It fired a false positive when W^X was enabled.

Also, reuse emitOutputLong instead of creating our own for RISC-V.

Part of #84834
cc @wscho77@HJLeee@clamp03@JongHeonChoi@t-mustafin@gbalykov@viewizard@ashaurtaev@brucehoult@sirntar@yurai007@Bajtazar

Author:tomeksowi
Assignees:-
Labels:

area-CodeGen-coreclr

Milestone:-

@clamp03clamp03 added the arch-riscv Related to the RISC-V architecture label Feb 15, 2024
Comment threadsrc/coreclr/jit/emitriscv64.cpp Outdated
@ryujit-bot

Copy link
Copy Markdown
Diff results for #98484

Throughput diffs

Throughput diffs for linux/arm64 ran on windows/x64

MinOpts (-0.01% to +0.00%)
CollectionPDIFF
libraries.pmi.linux.arm64.checked.mch-0.01%

Throughput diffs for osx/arm64 ran on windows/x64

MinOpts (-0.00% to +0.01%)
CollectionPDIFF
realworld.run.osx.arm64.checked.mch+0.01%

Throughput diffs for windows/arm64 ran on windows/x64

MinOpts (-0.01% to +0.00%)
CollectionPDIFF
realworld.run.windows.arm64.checked.mch-0.01%

Details here


There shouldn't be a problem when we introduce compressed instructions, VF2 supports unaligned stores (sw)
Also, replace compile-time conditions with static_asserts.
@ryujit-bot

Copy link
Copy Markdown
Diff results for #98484

Throughput diffs

Throughput diffs for osx/arm64 ran on windows/x64

MinOpts (-0.00% to +0.01%)
CollectionPDIFF
realworld.run.osx.arm64.checked.mch+0.01%

Throughput diffs for windows/arm64 ran on windows/x64

MinOpts (-0.01% to +0.00%)
CollectionPDIFF
realworld.run.windows.arm64.checked.mch-0.01%

Details here


@ryujit-bot

Copy link
Copy Markdown
Diff results for #98484

Throughput diffs

Throughput diffs for osx/arm64 ran on windows/x64

MinOpts (-0.00% to +0.01%)
CollectionPDIFF
realworld.run.osx.arm64.checked.mch+0.01%

Throughput diffs for windows/arm64 ran on windows/x64

MinOpts (-0.00% to +0.01%)
CollectionPDIFF
libraries.pmi.windows.arm64.checked.mch+0.01%

Details here


@tomeksowi
tomeksowi marked this pull request as ready for review February 15, 2024 21:36

@bartlomiejkobartlomiejko left a comment

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

Comment threadsrc/coreclr/jit/emitriscv64.cpp Outdated
@ryujit-bot

Copy link
Copy Markdown
Diff results for #98484

Throughput diffs

Throughput diffs for linux/arm64 ran on windows/x64

MinOpts (-0.01% to +0.00%)
CollectionPDIFF
libraries.pmi.linux.arm64.checked.mch-0.01%
realworld.run.linux.arm64.checked.mch-0.01%

Details here


@brucehoult

Copy link
Copy Markdown

LGTM

@github-actionsgithub-actionsBot locked and limited conversation to collaborators Apr 1, 2024
Sign up for freeto subscribe to this conversation on GitHub. Already have an account? Sign in.

Labels

arch-riscvRelated to the RISC-V architecturearea-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects

None yet

Development

Successfully merging this pull request may close these issues.

8 participants

@tomeksowi@ryujit-bot@brucehoult@clamp03@jakobbotsch@yurai007@sirntar@bartlomiejko