cpuid Package Documentation

The cpuid package provides a comprehensive set of functions and data structures to query detailed information about the host CPU. It supports multiple architectures and operating systems, enabling you to identify the CPU vendor, supported features, caches, TLB configurations, and more.

Supported Platforms

Architecture	OS	Notes
x86 (386)	Linux, Darwin, Windows	Full CPUID instruction support
x86_64 (amd64)	Linux, Darwin, Windows	Full CPUID instruction support
ARM	Linux	MIDR-based identification
ARM64	Linux	MIDR-based identification
ARM64	Darwin (macOS)	Apple Silicon support via sysctl

Supported Vendors

x86/x86_64:

• Intel (GenuineIntel)
• AMD (AuthenticAMD)

ARM/ARM64:

• ARM Ltd.
• Broadcom
• Cavium
• DEC
• NVIDIA
• APM
• Qualcomm
• Marvell

Apple Silicon:

• M1, M1 Pro, M1 Max, M1 Ultra
• M2, M2 Pro, M2 Max, M2 Ultra
• M3, M3 Pro, M3 Max, M3 Ultra
• M4, M4 Pro, M4 Max, M4 Ultra

Installation

go get github.com/earentir/cpuid

Key Features

• Vendor Identification - Detects CPU vendor (Intel, AMD, Apple, ARM, etc.)
• CPU Model and Family - Retrieves raw and effective CPU family, model, stepping IDs
• Brand String - Extracts the full human-readable CPU name
• Core and Thread Topology - Determines cores, threads, and topology information
• Addressing Capabilities - Physical and linear address bits
• Feature Detection - Comprehensive CPU feature flags across multiple categories
• Cache Information - Details about L1, L2, L3 caches
• TLB Details - Translation Lookaside Buffer configuration
• Intel Hybrid CPU Support - P-core and E-core detection
• Apple Silicon Support - Detailed Apple chip information including performance/efficiency cores
• Offline Mode - Analyze CPUID data from JSON files

Data Types

CPUCacheInfo

Stores information about CPU cache levels.

typeCPUCacheInfostruct {
Leveluint32// Cache level (1, 2, 3)Typestring// "Data", "Instruction", or "Unified"SizeKBuint32// Size in kilobytesWaysuint32// Associativity (ways)LineSizeBytesuint32// Cache line sizeTotalSetsuint32// Number of setsMaxCoresSharinguint32// Maximum cores sharing this cacheFlagsuint32// Cache flagsSelfInitializingbool// Self-initializing cacheFullyAssociativebool// Fully associative cacheMaxProcessorIDsuint32// Maximum processor IDsWritePolicystring// "Write Back", "Write Through", etc.
}

ProcessorModel

Stores processor model information.

typeProcessorModelstruct {
SteppingIDuint32// Stepping IDModelIDuint32// Model IDFamilyIDuint32// Family IDProcessorTypeuint32// Processor typeExtendedModelIDuint32// Extended model IDExtendedFamilyIDuint32// Extended family IDExtendedModeluint32// Computed effective modelExtendedFamilyuint32// Computed effective family
}

ProcessorInfo

Stores basic CPU information.

typeProcessorInfostruct {
MaxLogicalProcessorsuint32// Maximum logical processorsInitialAPICIDuint32// Initial APIC IDPhysicalAddressBitsuint32// Physical address bitsLinearAddressBitsuint32// Linear address bitsCoreCountuint32// Number of coresThreadPerCoreuint32// Threads per core
}

TLBInfo

Stores TLB configuration.

typeTLBInfostruct {
Vendorstring// CPU vendorL1TLBLevel// L1 TLB infoL2TLBLevel// L2 TLB infoL3TLBLevel// L3 TLB info
}
typeTLBLevelstruct {
Data []TLBEntry// Data TLB entriesInstruction []TLBEntry// Instruction TLB entriesUnified []TLBEntry// Unified TLB entries
}
typeTLBEntrystruct {
PageSizestring// Page size (e.g., "4KB", "2MB", "1GB")Entriesint// Number of entriesAssociativitystring// Associativity description
}

IntelHybridInfo

Stores Intel hybrid CPU information.

typeIntelHybridInfostruct {
HybridCPUbool// Is hybrid CPUNativeModelIDuint32// Native model IDCoreTypeuint32// Core type codeCoreTypeNamestring// "Performance core (P-core)" or "Efficient core (E-core)"
}

AppleSiliconInfo (darwin/arm64 only)

Stores Apple Silicon specific information.

typeAppleSiliconInfostruct {
ChipNamestring// e.g., "Apple M4 Pro"Generationint// 1, 2, 3, or 4Variantstring// "Base", "Pro", "Max", or "Ultra"PerformanceCoresint// Number of P-coresEfficiencyCoresint// Number of E-coresTotalCoresint// Total coresMemorySizeint64// Memory size in bytesHasNeuralEnginebool// Neural Engine supportHasProResSupportbool// ProRes supportHasThunderboltbool// Thunderbolt supportMaxMemoryBandwidthstring// Memory bandwidth
}

Entry and Data (for offline mode)

typeEntrystruct {
Leafuint32`json:"leaf"`Subleafuint32`json:"subleaf"`EAXuint32`json:"eax"`EBXuint32`json:"ebx"`ECXuint32`json:"ecx"`EDXuint32`json:"edx"`
}
typeDatastruct {
Entries []Entry`json:"entries"`
}

Important Functions

Vendor Information

funcGetVendorID(offlinebool, filenamestring) string

Returns the CPU vendor ID string (e.g., "GenuineIntel", "AuthenticAMD", "Apple").

funcGetVendorName(offlinebool, filenamestring) string

Returns the human-readable vendor name (e.g., "Intel", "AMD", "Apple").

Brand and Model

funcGetBrandString(maxExtFuncuint32, offlinebool, filenamestring) string

Returns the full CPU brand string (e.g., "Intel(R) Core(TM) i9-12900K").

funcGetModelData(offlinebool, filenamestring) ProcessorModel

Returns processor model information including family, model, and stepping.

Processor Information

funcGetMaxFunctions(offlinebool, filenamestring) (uint32, uint32)

Returns maximum supported standard and extended CPUID function values.

funcGetProcessorInfo(maxFunc, maxExtFuncuint32, offlinebool, filenamestring) ProcessorInfo

Returns detailed processor information including core count and addressing capabilities.

funcGotEnoughCores(coreCountuint32, realcoresbool, offlinebool, filenamestring) bool

Checks if the CPU has at least the specified number of cores.

Cache and TLB

funcGetCacheInfo(maxFunc, maxExtFuncuint32, vendorIDstring, offlinebool, filenamestring) ([]CPUCacheInfo, error)

Returns cache information for all cache levels.

funcGetTLBInfo(maxFunc, maxExtFuncuint32, offlinebool, filenamestring) (TLBInfo, error)

Returns TLB configuration for L1, L2, and L3.

Feature Detection

funcGetAllFeatureCategories() []string

Returns all available feature categories.

funcGetAllFeatureCategoriesDetailed() map[string][]map[string]string

Returns detailed information about all features in all categories.

funcGetAllKnownFeatures(categorystring) []string

Returns all known features for a given category.

funcGetSupportedFeatures(categorystring, offlinebool, filenamestring) []string

Returns all features supported by the current CPU in a given category.

funcIsFeatureSupported(featureNamestring, offlinebool, filenamestring) bool

Checks if a specific feature is supported.

Intel Hybrid CPU

funcGetIntelHybrid(offlinebool, filenamestring) IntelHybridInfo

Returns hybrid CPU information (works for both Intel and Apple Silicon).

Apple Silicon (darwin/arm64 only)

funcGetAppleSiliconInfo() AppleSiliconInfo

Returns detailed Apple Silicon information.

funcGetAppleSiliconFeatures() []string

Returns all features supported by Apple Silicon.

funcIsAppleSiliconFeatureSupported(featurestring) bool

Checks if a specific Apple Silicon feature is supported.

Data Capture (Offline Mode)

funcCaptureData(filenamestring) error

Captures all CPUID data and saves to a JSON file.

funcDataFromFile(filenamestring) (Data, error)

Loads CPUID data from a JSON file.

Feature Categories (x86/x86_64)

The package supports detection of 49+ feature categories with hundreds of individual features for Intel and AMD processors:

Category	Description	Features
StandardECX	Standard Features (ECX register)	SSE3, PCLMULQDQ, MONITOR, VMX, SMX, SSSE3, FMA, SSE4.1, SSE4.2, AES, AVX, F16C, RDRAND, and more
StandardEDX	Standard Features (EDX register)	FPU, VME, DE, PSE, TSC, MSR, PAE, MCE, APIC, SEP, MTRR, MMX, SSE, SSE2, HTT, and more
ExtendedEBX	Extended Features (EBX register)	FSGSBASE, BMI1, AVX2, BMI2, ERMS, INVPCID, AVX512F, AVX512DQ, RDSEED, SHA, AVX512BW, AVX512VL, and more
ExtendedECX	Extended Features (ECX register)	PREFETCHWT1, AVX512_VBMI, UMIP, PKU, VAES, VPCLMULQDQ, AVX512_VNNI, LA57, RDPID, and more
AMDExtendedECX	AMD Extended Features	LAHF_LM, SVM, ABM, SSE4A, 3DNOWPREFETCH, IBS, XOP, FMA4, TBM, MWAITX, and more
PowerManagement	Power Management	DTHERM, IDA, ARAT, HWP, HDC, TURBO3, CPB, RAPL, and more
SGX	Software Guard Extensions	SGX1, SGX2, ENCLV, ENCLS, ENCLU, SEV, SEV_ES, SEV_SNP, and more
PT	Processor Trace	CR3_FILTERING, PSB, IP_FILTERING, MTC, PTWRITE, and more
MTRR	Memory Type Range Registers	MTRR_VCNT, MTRR_FIX, MTRR_WC, MTRR_SMRR, and more
CacheFeatures	Cache Properties	CACHE_SELF_SNOOP, CACHE_INCLUSIVENESS, WBINVD, and more
XSave	Extended State (XSAVE)	XSAVEOPT, XSAVEC, XGETBV_ECX1, XSAVES, XFD, and more
PerformanceMonitor	Performance Monitoring	PMC counters, PEBS, LBR, core cycles, instructions retired, and more
Virtualization	Virtualization	VMX, EPT, VPID, SVM, NPT, VMCB_CLEAN, and more
ExtendedSecurity	Security Features	SMAP, SMEP, UMIP, IBT, SHSTK, CET_IBT, SEV, SEV_SNP, and more
PlatformSecurity	Platform Security	TPM, SKINIT, SEV, SME, VMPL, SGX_LC, and more
ExtendedDebug	Debug Features	LBR, PEBS, IPT, BTS, IBS_FETCH, IBS_OP, and more
AdvancedMatrixExtensions	AMX Features	AMX_BF16, AMX_TILE, AMX_INT8, AMX_FP16, and more
SMM	System Management Mode	SMM_MONITOR, SMM_VMCALL, SMM_LOCK, SKINIT, and more
Real-TimeInstructions	Real-Time Instructions	HRESET, LAM, FRED, LKGS, MWAITX, MONITORX, and more
CoreThread	Core & Thread	APIC_IDS, CORE_COUNT, HYBRID_ARCH, CCD_ID, CCX_ID, and more
ErrorDetection	Error Detection	MCA, MCE, DEP, SUCCOR, SCALABLE_MCA, and more
Prefetch	Prefetch Features	PREFETCHW, PREFETCHWT1, 3DNOW_PREFETCH, and more
BUS	Bus Features	BUS_LOCK_DETECT, SPLIT_LOCK_DETECT, QOS_ENF, and more
ApplicationTargeted	Application Features	WAITPKG, KEYLOCKER, HFI, FAST_SHORT_REP, and more
Encryption	Encryption	AES_128, AES_256, VAES, SHA_1, SHA_256, SHA_512, GFNI, KL, and more
SpeculationControl	Speculation Control	IBRS, STIBP, SSBD, IBPB, L1D_FLUSH, MD_CLEAR, and more
BranchPrediction	Branch Prediction	IBC, IBPB_BRTYPE, SRSO, BHI_CTRL, BHB_CLEAR, and more
VectorNeuralNetwork	Neural Network	AVX512_4VNNIW, AVX512_4FMAPS, AMX_BF16, AVX_VNNI, and more
TransactionalSynchronization	TSX	TSX_HLE, TSX_RTM, TSX_CTRL, RTM_ALWAYS_ABORT, and more
NestedVirtualization	Nested Virtualization	NPT, NRIPS, VMCB_CLEAN, VGIF, VMX_EPT, SHADOW_VMCS, and more
MemoryBandwidth	Memory Bandwidth	RDT_M, RDT_A, MBA, CQM, L3_MONITORING, and more
AdvancedPowerManagement	Advanced Power	APM_CNT, WDT, HWPS, TSC_INVARIANT, CPB, RAPL, and more

Apple Silicon Features (darwin/arm64)

Category	Features
ARM Standard	NEON, FP16, CRC32, AES, SHA1, SHA256, PMULL, ATOMICS, ASIMD, FCMA, JSCVT, LRCPC, DPB, DPB2, FRINTTS, SB, SSBS, BTI, FHM, DIT, FP, ASIMD_HP, ASIMD_DP, ASIMDFHM, AMX
M3/M4 Specific	RAYTRACING, MESH_SHADING, DYNAMIC_CACHING
M4 Specific	SME, SME2, SVE2, FP8

Usage Examples

Basic Usage

package main
import (
"fmt""github.com/earentir/cpuid"
)
funcmain() {
// Get vendor informationvendorID:=cpuid.GetVendorID(false, "")
vendorName:=cpuid.GetVendorName(false, "")
fmt.Printf("Vendor: %s (%s)\n", vendorName, vendorID)
// Get brand stringmaxFunc, maxExtFunc:=cpuid.GetMaxFunctions(false, "")
brand:=cpuid.GetBrandString(maxExtFunc, false, "")
fmt.Printf("Brand: %s\n", brand)
// Get processor infoinfo:=cpuid.GetProcessorInfo(maxFunc, maxExtFunc, false, "")
fmt.Printf("Cores: %d, Threads per core: %d\n", info.CoreCount, info.ThreadPerCore)
// Check feature supportifcpuid.IsFeatureSupported("AVX2", false, "") {
fmt.Println("AVX2 is supported!")
}
}

Cache Information

caches, err:=cpuid.GetCacheInfo(maxFunc, maxExtFunc, vendorID, false, "")
iferr==nil {
for_, cache:=rangecaches {
fmt.Printf("L%d %s Cache: %d KB, %d-way, %d byte line\n",
cache.Level, cache.Type, cache.SizeKB, cache.Ways, cache.LineSizeBytes)
}
}

Feature Categories

// List all categoriescategories:=cpuid.GetAllFeatureCategories()
for_, cat:=rangecategories {
features:=cpuid.GetSupportedFeatures(cat, false, "")
fmt.Printf("%s: %v\n", cat, features)
}

Offline Mode (Analyze captured data)

// Capture current CPU dataerr:=cpuid.CaptureData("mycpu.json")
// Later, analyze offlinevendorID:=cpuid.GetVendorID(true, "mycpu.json")
features:=cpuid.GetSupportedFeatures("StandardECX", true, "mycpu.json")

Apple Silicon Specific

// On macOS with Apple Siliconinfo:=cpuid.GetAppleSiliconInfo()
fmt.Printf("Chip: %s (Generation %d, %s)\n", info.ChipName, info.Generation, info.Variant)
fmt.Printf("Performance Cores: %d, Efficiency Cores: %d\n",
info.PerformanceCores, info.EfficiencyCores)
features:=cpuid.GetAppleSiliconFeatures()
fmt.Printf("Supported features: %v\n", features)

License

See LICENSE file for details.