RISC-V

RISC-V model built in SystemVerilog

This is an implementation of the basic 64 bit RISC-V ISA. Project is still in its early stages as of now. ALU is mostly done and working on instruction functionality

Name		Name	Last commit message	Last commit date
ALU.sv		ALU.sv
ALU_Control.sv		ALU_Control.sv
ALU_TB.sv		ALU_TB.sv
Array_Multiplier.sv		Array_Multiplier.sv
CLA_4bit.sv		CLA_4bit.sv
CLA_64bit.sv		CLA_64bit.sv
CLA_64bit_TB.sv		CLA_64bit_TB.sv
CPU_Core.sv		CPU_Core.sv
CPU_Core_TB.sv		CPU_Core_TB.sv
Dadda_Multiplier.sv		Dadda_Multiplier.sv
Divider.sv		Divider.sv
Full_Adder.sv		Full_Adder.sv
Half_Adder.sv		Half_Adder.sv
Include_Files.sv		Include_Files.sv
Practice_Dadda.py		Practice_Dadda.py
README.md		README.md
Subtractor_64bit.sv		Subtractor_64bit.sv
abs.sv		abs.sv
parameters.sv		parameters.sv
register		register
register.sv		register.sv

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