TRI-1 Phi — Trinity φ-anchor (Canonical Seed + Lucas POST)

One of three neurons of Trinity TRI-NET — three sacred constants embodied in silicon:
φ-anchor → THIS REPO (1×1, Lucas POST checking φ²+φ⁻²=3, CLARA Gap-4)
e-engine → tt-trinity-euler (8×2, 18 SUPER-CROWN modules)
γ-surface → tt-trinity-gamma (8×4, 32 PE full mesh)
Apache-2.0 · ternary {−1,0,+1} · SKY130A · DOI 10.5281/zenodo.19227877

TL;DR

What this repo is.tt-trinity-phi is the φ-anchor: the smallest, 1×1 Tiny Tapeout chip of the TRI-NET line. It is the reference identity / proof-seed / silicon-provenance SKU — the chip the other two TRI-NET dies anchor against. Open PDK (SKY130A), Apache-2.0 RTL.
What runs today. Canonical GF16(2⁴) dot4(1.0, 2.0, 3.0, 4.0) = 0x47C0 on {uio_out, uo_out} at reset; Lucas L₂..L₇ POST checking the identity φ²+φ⁻²=3; CLARA Gap-4 restraint_ctrl; die-unique HWRNG; friend/foe handshake; v1.0.0 GF4..GF256 / quantizer / power-module RTL. CI gates: iverilog canonical test, cocotb suite, Yosys synth, Verilator lint, R-SI-1 no-* audit, OpenLane2 SKY130A GDS. Submitted to TTSKY26b shuttle (see CHANGELOG.md).
How to verify.iverilog -I src -o /tmp/tb.out src/*.v test/tb.v && vvp /tmp/tb.out (expect 0x47C0). Workflows in .github/workflows/ reproduce the same checks on every push. Full reproduction recipes are in BENCHMARKS.md.
Why this is unique. Open SKY130A + Apache-2.0 RTL · ternary / GoldenFloat research path · CLARA-aligned formal-assurance trace · reproducible .t27 → RTL → shuttle pipeline. Not a peak-TOPS competitor to commercial NPUs — see COMPETITORS.md for the honest positioning.
Documentation package.STATUS.md (readiness ladder) · LINEUP.md (TRI-NET positioning) · CLARA_TRACEABILITY.md (assurance evidence map) · COMPETITORS.md · BENCHMARKS.md.
Next-lineup spec docs (draft, planned-only items clearly labelled).D2D_PROTOCOL.md (φ-anchor role in chip-to-chip) · GF16_BFLOAT16_NMSE.md (NMSE comparison contract) · TRIPLE_DECK_STATUS.md (RBB / FBB / CAP_BOOST honest status — only FBB is in RTL on φ-anchor today) · TRI_NET_API.md (external-integration index) · WHITEPAPER.md (value-proposition hub) · TOPS_W_22FDX_PROJECTION.md (22FDX projection + Zenodo bundle plan) · docs/SCIENTIFIC_IMPROVEMENT_PLAN.md (2026 plan — CL / EN / SN / PUB / OS tracks, all targets labelled) · .github/issues/ (filing pack: 1 EPIC + 16 child issues, IDs #0..#16 are local placeholders until create_issues.sh mints GitHub numbers).
Verification hardening layer (this PR).docs/VERIFICATION_CLAIMS_MATRIX.md (every numerical claim + anti-claim, indexed by VC-* IDs) · docs/vectors/nmse/ (golden NMSE reference vectors — not silicon captures) · conformance/d2d/ (5 D2D conformance vectors: valid header, bad CRC, unsupported opcode, timeout/retry, multi-chip ordering) · docs/TRIPLE_DECKER_STATE_MACHINE.md (IDLE → RBB → FBB → CAP_BOOST → IDLE + brownout/overcurrent fallback) · docs/ARCHITECTURE_QUICK_WINS.md (competitor-informed, repo-grounded next steps) · docs/RELEASE_MANIFEST_TRINET_V1.md (intended Zenodo deposition manifest — DOI not yet minted for this release) · scripts/check_trinet_specs.sh + .github/workflows/spec-gate.yml (spec CI gate).
Siblings.tt-trinity-euler (8×2 e-engine safety/control) · tt-trinity-gamma (8×4 γ-surface 32-PE mesh) · t27 toolchain + numeric registry (specs/numeric/).

TRI-NET Positioning

TRI-NET — verifiable open silicon stack for trustworthy AI: identity (Φ), reasoning (E), inference (Γ). One math anchor, three chips, zero closed IP.

Φ Identity Layer — Root of Trust

tt-trinity-phi is the identity foundation of the TRI-NET stack. As the smallest die (1×1 tile, 51 modules, 6132 lines of RTL), Phi's singular mission is attestation: proving at power-up that this silicon is what it claims to be. The Lucas POST sequence (phi_anchor_post) checks the identity φ²+φ⁻²=3 in hardware via discrete recurrence (the identity is a theorem; the POST verifies the silicon reproduces it), the hwrng_lfsr generates a die-unique nonce for each boot, and restraint_ctrl enforces CLARA Gap-4 bounded rationality. Phi carries the DePIN accumulator (tri_token_accumulator) and the Mesh-lite v1.1.0 E/W bi-port bridge for die-to-die connectivity.

In the TRI-NET trust model, Phi answers the question: "I exist, I have not been substituted, and my boot reproduces the expected anchor." It is the root every higher layer anchors against — Euler's reasoning layer and Gamma's inference surface both chain their attestation receipts to the identity anchor Phi reproduces on reset (a deterministic POST / provenance fingerprint, not a cryptographic proof).

Cross-Die Anchor 0x47C0 — Theorem 36.1

Every TRI-NET die asserts {uio_out, uo_out} = 0x47C0 on reset. This value is not a magic constant — it is derived from first principles: φ²+φ⁻²=3 (the Lucas L₂ identity) implies dot4(1,2,3,4) = 0x47C0 in GF16. This derivation is formalised as PhD Theorem 36.1 (Chapter 36, flos_70.tex). Because all three dies independently compute the same anchor from the same mathematical identity, a multi-chip board can use it as a deterministic POST / build-provenance fingerprint without any shared secret — this is a liveness/provenance check, not a cryptographic proof of correctness (a returned die emitting a value ≠ 0x47C0 would refute shared provenance). DOI: 10.5281/zenodo.19227877.

"The boot you can verify."

Sibling Chips

Chip	Role	Repository
Φ Phi (this repo)	Identity Layer — Root of Trust	tt-trinity-phi
E Euler	Reasoning Layer — Verifiable AI Safety (10 CLARA Gaps)	tt-trinity-euler
Γ Gamma	Inference Layer — Neuromorphic Surface	tt-trinity-gamma

TRI-NET vs. Alternatives — What Others Cannot Offer

Property	TRI-NET	Tenstorrent	Etched	Groq
Open RTL (Apache-2.0)	✅	partial	❌	❌
Math-anchored boot (Lucas POST)	✅	❌	❌	❌
CLARA AI Safety Gaps (hardware)	✅ 10 gaps	❌	❌	❌
On-die DePIN token accumulator	✅	❌	❌	❌
Cross-die canonical anchor 0x47C0	✅ Theorem 36.1	❌	❌	❌
Sub-$50 SKU	✅ Phi ~$2.50	❌	❌	❌

TRI-NET competes on verifiability/$, not TOPS/$. Performance reference: ~1 GOPS @ ~50 MHz @ ~1 W ternary (projected).

Verification & Reproducibility

This repo ships a machine-checkable verification layer on top of the RTL. Every numerical claim in the docs/specs has a row in docs/VERIFICATION_CLAIMS_MATRIX.md with an explicit Claim ID, Location, Evidence/Witness, Harness, Status, and Anti-claim. The spec gate scripts/check_trinet_specs.sh (wired into CI via .github/workflows/spec-gate.yml) refuses to ship a number that does not have a matrix row.

Claim status legend

The matrix and all R5-honest docs in this repo use this five-tier legend. Mixing tiers across the same table is a spec violation.

Mark	Tier	Meaning
✓	MEASURED (silicon)	Result is from a fabricated, characterised die. No row in this repo is MEASURED-silicon today.
⊙	PRE-SILICON simulation	Result is from a CI workflow that exercises real RTL via iverilog / cocotb / Yosys / Verilator / OpenLane2 in this repo.
◷	PROJECTED (architectural)	Result is derived from RTL intent or first-principles scaling; no PVT-anchored simulation yet.
▢	SPEC	Result is a contract that the harness must match once it exists; no run has happened.
✗	NOT MEASURED (anti-claim)	Result is deliberately not claimed; the matrix preserves the absence (e.g., `VC-NM-1` no silicon TOPS/W).

These tiers map directly onto MLCommons measurement methodology and the silicon-evidence framing used by IBM NorthPole, Google Edge TPU, and NVDLA — see docs/ARCHITECTURE_QUICK_WINS.md for the cross-walk.

Verification assets shipped today

Asset	Path	Purpose
Claims matrix	`docs/VERIFICATION_CLAIMS_MATRIX.md`	Normative index of every numerical claim with anti-claims.
Golden NMSE vectors	`docs/vectors/nmse/gf16_vs_bfloat16.golden.json`	Seeded reference baselines + tolerances for GF16 vs bf16; `provenance.mode = RTL_ONLY`, no silicon.
D2D conformance	`conformance/d2d/`	5 vectors: `valid_header.json`, `bad_crc.json`, `unsupported_opcode.json`, `timeout_retry.json`, `multi_chip_ordering.json`.
Triple-Decker FSM	`docs/TRIPLE_DECKER_STATE_MACHINE.md`	`IDLE → RBB → FBB → CAP_BOOST → IDLE` + brownout/overcurrent fallback.
Quick-wins map	`docs/ARCHITECTURE_QUICK_WINS.md`	phi-specific, competitor-informed next steps grounded in `src/`.
Release manifest	`docs/RELEASE_MANIFEST_TRINET_V1.md`	Intended Zenodo deposition contents (DOI not yet minted for this release).
Spec gate (local + CI)	`scripts/check_trinet_specs.sh`, `.github/workflows/spec-gate.yml`	Schema-checks vectors, enforces R5 honesty, validates VC- citations.
Zenodo metadata	`.zenodo.json`	Metadata template for the next deposition; placeholder DOIs marked `TBD`.

Reproduce the spec gate locally

bash scripts/check_trinet_specs.sh
# expect: OK: TRI-NET spec gate passed.

Python 3 is the only host dependency (used for JSON schema checks). The optional t27c parser is exercised if on PATH; the gate skips it cleanly when absent.

Zenodo / DOI status

The existing line-level DOI 10.5281/zenodo.19227877 anchors the prior TRI-NET Trinity-Stack bundle. The verification hardening layer on this branch is part of a future deposition whose DOI has not yet been minted. docs/RELEASE_MANIFEST_TRINET_V1.md and .zenodo.json describe the intended metadata; any table that quotes a DOI for this release before deposition is published is an R5 violation. The matrix anti-claim VC-NM-6 is the source of truth.

Quick Start

Prerequisites

# Install Verilog tools
brew install iverilog cocotb
# Clone phi-anchor
git clone https://github.com/gHashTag/tt-trinity-phi

Simulation

cd tt-trinity-phi
iverilog -I src -o test/tb.out src/*.v test/tb.v
vvp test/tb.out
# Expected: canonical 0x47C0 output

GDS Synthesis

git push
# Triggers .github/workflows/gds.yaml# OpenLane2 (SKY130A) → DRC + LVS + STA → uploads gds_artifact

What is φ-anchor?

φ-anchor is the golden foundation of Trinity TRI-NET — the smallest, simplest, most-likely-to-tape-out cleanly member of the three sacred constants:

Neuron	Constant	Tiles	Modules	Role
φ-anchor	φ ≈ 1.61803	1×1	13	golden foundation — must close
e-engine	e ≈ 2.71828	8×2	18 SUPER-CROWN	expansion layer
γ-surface	γ ≈ 0.57721	8×4	24 SUPER-CROWN	neuromorphic surface

φ ≈ 1.61803 (golden ratio) is the fundamental constant that governs growth patterns in nature.

All three TRI-NET dies emit the same canonical 0x47C0 on power-up, computed from dot4(1.0, 2.0, 3.0, 4.0) in GF16.

Sacred Formula

V = n × 3^k × π^m × φ^p × e^q × γ^r × C^t × G^u

This chip is the φ^p factor — the golden anchor.

Identity: φ² + φ⁻² = 3 (Trinity identity)

Architecture

Single-Tile Structure

 ┌────────────────────────────────────────────────┐
ui_in[0] │ tt_um_trinity_phi (top) │
load_mode ───►│ │
ui_in[7] │ ┌─────────────────────────────────────────┐ │
load_strobe ─►│ │ canonical gf16_dot4(1,2,3,4) = 0x47C0 │ │ ──► uo_out[7:0] = 0xC0
ui_in[6] │ │ (combinational, always live) │ │ uio_out[7:0] = 0x47
compute_s ───►│ └─────────────────────────────────────────┘ │
│ │
ui_in[3:1] │ ┌─────────────────────────────────────────┐ │
lucas_idx ───►│ │ phi_anchor_post (Lucas L₂..L₇ POST) │ │ ──► phi_ok, post_done
ui_in[4] │ │ lucas_rom (addressable L_n) │ │ ──► POST status byte
rng_ena ─────►│ │ hwrng_lfsr (die-unique nonce) │ │
ui_in[5] │ │ restraint_ctrl (CLARA Gap-4) │ │
restraint ───►│ └─────────────────────────────────────────┘ │
│ │
uio_in[7:0] │ ┌─────────────────────────────────────────┐ │
operand ─────►│ │ trinity_gf16_tile #(TILE_ID=0) │─┼──► uo_out / uio_out
│ │ packet path (LOAD_A, COMPUTE, RESULT) │ │ when load_mode=1
│ └─────────────────────────────────────────┘ │
└────────────────────────────────────────────────┘

Enhanced Modules (v2)

Module	Function	Cells	Purpose
`gf16_dot4.v`	Canonical 0x47C0 anchor	~50	Cross-die TG-TRIAD-X
`gf16_mul.v`	XOR-based GF16 multiply	~50	R-SI-1 compliant (0 DSP)
`trinity_gf16_tile.v`	Packet-path compute tile	~250	Full TRN protocol
`phi_anchor_post.v`	Lucas L₂..L₇ POST	~120	Checks φ²+φ⁻²=3 at reset
`lucas_rom.v`	Addressable L_n probe	~30	Host verification
`hwrng_lfsr.v`	16-bit die-unique nonce	~20	Chaotic entropy
`restraint_ctrl.v`	CLARA Gap-4 bounded rationality	~100	AI safety
`sacred_constants_rom.v`	75 PhD constants (sparse)	~133	Glava 3+7+28
`crown47_rom.v`	47 Trinity constants	~100	Crown of TRI-NET
`trinity_friend_foe.v`	D2D handshake (MY_ANCHOR=φ)	~30	Mesh identity
`gf16_add.v`	GF16 addition	~20	Arithmetic

Total estimated cells: ~850 @ 60% density

Lucas POST

Algorithm

Checks the identity φ²+φ⁻²=3 via discrete Lucas recurrence:

L₁ = 1, L₂ = 3
L_{n+1} = L_n + L_{n-1}
POST checks: L₂=3, L₃=4, L₄=7, L₅=11, L₆=18, L₇=29

Any mismatch latches phi_ok=0 (sticky-low POST failure).

By Binet's Formula

By Binet's formula on Lucas numbers: L₂ = φ² + φ⁻² = 3

The identity L₂ = φ² + φ⁻² = 3 is a theorem (Binet); the POST checks that the silicon reproduces it bit-exactly at reset — an attestation/provenance check, not a new mathematical proof.

Sacred ROMs

Sacred Constants ROM (75 cells)

Stores PhD constants (Glava 3, Glava 7, Glava 28) with sparse encoding.

Constant	Value	Purpose
φ (phi)	0.8090 (Q1.15)	Golden ratio (Q1.15)
φ²	1.6180 (Q2.30)	φ² (Q2.30)
γ (gamma)	0.2886 (Q0.58)	Euler-Mascheroni
C	0.5	Speed of light constant
G	1.0	Gravitational constant

Crown47 ROM (100 cells)

Stores 47 Trinity constants used across all TRI-NET dies.

Build & Test

Local Simulation

cd tt-trinity-phi
iverilog -I src -o test/tb.out src/*.v test/tb.v
vvp test/tb.out

Expected: canonical 0x47C0 output on {uio_out, uo_out}.

GDS Synthesis

git push
# → triggers .github/workflows/gds.yaml# → OpenLane2 (SKY130A) → DRC + LVS + STA → uploads gds_artifact

Pin Mapping

Pin	Function	Description
`ui_in[0]`	load_mode	0=canonical/POST, 1=packet path
`ui_in[3:1]`	lucas_idx	3-bit Lucas ROM address
`ui_in[4]`	rng_ena	Advance HWRNG LFSR when high
`ui_in[5]`	restraint_mode	CLARA Gap-4 active
`ui_in[6]`	compute_strobe	Rising edge issues COMPUTE
`ui_in[7]`	load_lane_strobe	Rising edge advances lane
`uo_out[7:0]`	result[7:0]	GF16 result bytes
`uio_out[7:0]`	result[15:8]	GF16 result bytes or POST status

POST Status Byte (post_done=1, load_mode=0)

Bit	Field	Value
`uo_out[7]`	phi_post_ok	1=POST passed, 0=failed
`uo_out[6]`	phi_post_done	1=POST complete
`uo_out[5:0]`	lucas_val[5:0]	Selected Lucas value

⚡ Performance Benchmarks

Tier labels for this section. All Throughput / Latency / Area / Power rows below are ⊙ PRE-SILICON simulation (iverilog/cocotb) or ◷ PROJECTED (architectural). No row is ✓ MEASURED-silicon. The exact tier and witness for each numerical claim lives in docs/VERIFICATION_CLAIMS_MATRIX.md; the matrix is the source of truth and the spec gate refuses ungrounded claims.

Throughput

Operation	Clock cycles	Throughput @50MHz	Notes
GF16 dot4	1 (combinational)	50 MHz	Canonical anchor
GF16 add	1 (combinational)	50 MHz	Ternary-ready
GF16 mul	3 cycles	16.7 MHz	Partial-products
Lucas POST	8 cycles	6.25 MHz	L₂..L₇ check
HWRNG LFSR	1 cycle	50 MHz	Entropy source

Latency

Module	Latency	Notes
gf16_dot4	1 cycle	Pure combinatorial
gf16_add	1 cycle	Pure combinatorial
gf16_mul	3 cycles	Pipelined mantissa multiply
phi_anchor_post	8 cycles	POST verification
restraint_ctrl	2 cycles	CLARA Gap-4 bounded rationality

Area (SKY130A)

Component	Estimated cells	Utilization
Canonical anchor	~50	6%
Lucas POST chain	~150	18%
Sacred constants ROM	~133	16%
Crown47 ROM	~100	12%
v1.0.0 modules	~350	42%
Control + glue	~50	6%
Total	~833	70% of 1200

Power (SKY130A @50MHz)

Mode	Voltage	Power (mW)	Notes
Idle	0.75V	8 mW	Minimal leakage
Normal	0.95V	16 mW	Anchor compute
Burst	1.05V	32 mW	POST verification
AVS-96	0.75-1.05V	5-32 mW	6.4× adaptive range

v1.0.0 Performance Impact

Feature	Cells	Power impact	Performance impact
GF4-GF256 formats	~200	+1 mW	New arithmetic domains
Int4/Int8 quantizers	~80	+0.5 mW	4-8× memory bandwidth
NF4 quantizer	~30	+0.2 mW	QLoRA support
FP8 quantizers	~40	+0.3 mW	ML formats
Posit16 quantizer	~30	+0.2 mW	Dynamic precision
Sacred opcodes (11)	~50	+0.3 mW	AI safety + efficiency
AVS-96	~80	-6 mW (savings)	4× efficiency boost
FBB active path	~20	-2 mW (savings)	Leakage reduction
Purkinje thermal	~15	-1 mW (savings)	Bio-inspired cooling

Net v1.0.0 impact: -7 mW power reduction (4× efficiency gain).

Development Guide

R-SI Compliance Rules

Rule	Statement	How to Verify
R-SI-1	Zero `*` operators in RTL	`grep -n '\' src/.v`
R-SI-2	Zero DSP/multiplier macros	OpenLane2 reports
R-SI-3	WNS ≥ 0 ns @ 50 MHz	OpenLane2 STA
R-SI-4	DRC-clean	OpenLane2 KLayout DRC
R-SI-5	LVS-clean	OpenLane2 LVS
R-SI-6	Apache-2.0 only	`grep -i proprietary` (should be empty)

Adding Constants to Sacred ROM

Edit sacred_constants_rom.v
Verify sparse encoding (Q-format)
Run simulation: vvp test/tb.out
Check output matches expected constant

Verifying Lucas POST

# Simulate POST verification
iverilog -I src -o tb_post src/phi_anchor_post.v src/lucas_rom.v test/tb_post.v
vvp tb_post
# Should show: POST PASS - L2=3, L3=4, L4=7, L5=11, L6=18, L7=29

Contributing

We welcome contributions! Please:

Fork the repository
Create a feature branch (git checkout -b feature/amazing-feature)
Make your changes
Run tests (make test)
Commit your changes (git commit -m 'feat(...): ...')
Push to the branch (git push origin feature/amazing-feature)
Open a Pull Request

Code Review Checklist

Troubleshooting

Canonical Test Failure

If 0x47C0 is not emitted:

Check GF16 encoding:
```
iverilog -t null -I src src/gf16_dot4.v
```
Verify synthesis: yosys -p "read_verilog src/gf16_dot4.v; proc; stat"
Check timing with make test

GDS DRC Errors

# Check OpenLane2 reports
docker run -it --rm -v $(pwd):/work -w /work \
openlane2/openlane2:eula bash
openlane --config ./sky130A/config.tcl --run ./run_gds.tcl

POST Failure

Verify Lucas values match expected: L₁=1, L₂=3, L₃=4, L₄=7, L₅=11, L₆=18, L₇=29
Check phi_anchor_post.v implementation
Run standalone test: vvp tb_post

Competitive Analysis

No Competitor Has Native Ternary MAC

Competitor	Ternary MAC	Open PDK	Coq Verified	10 CLARA Gaps
Hailo-8	❌	❌	❌	❌
MediaTek NPU890	❌	❌	❌	❌
Qualcomm Cloud AI 100 Ultra	❌	❌	❌	❌
Axelera Metis M.2	❌	❌	❌	❌
Google Coral Edge TPU	❌	❌	❌	❌
φ-anchor	✅	✅	✅	1 (minimal)

Note: φ-anchor validates the base arithmetic layer. Full SUPER-CROWN capabilities (all 10 CLARA gaps) are in e-engine and γ-surface.

🏆 Competitive Differentiators

#	Differentiator	φ-anchor	e-engine	γ-surface
1	Native ternary {-1,0,+1} MAC	✅	✅	✅
2	On-chip BLAKE3 receipt signer	❌ (minimal)	✅	✅
3	POST via φ²+φ⁻²=3 Lucas chain	✅	✅	✅
4	0 DSP / 0 new `*` (R-SI-1)	✅	✅	✅
5	BitNet b1.58 ternary MLP	❌ (minimal)	✅	✅
6	RING27 3³ ternary memory	❌ (minimal)	✅	✅
7	Trinity 9-op ternary ALU (t27 ISA)	❌ (minimal)	✅	✅
8	On-chip BPB / cross-entropy	❌ (minimal)	✅	✅
9	Apache-2.0 + fully open PDK (SKY130A)	✅	✅	✅
10	DOI-anchored + Coq-verified	✅	✅	✅

Note: As the smallest (1×1) TRI-NET member, φ-anchor validates the base arithmetic layer + core safety features.

Green AI Manifesto

Honest Performance Disclosure (R5-HONEST)

Metric	Tier	Value	Matrix row
TOPS/W on SKY130A demonstrator	✗ NOT MEASURED	no silicon characterisation in repo	`VC-NM-1`
TOPS/W on 22FDX (architectural projection)	◷ PROJECTED	28–120 TOPS/W band (never a point estimate)	`VC-22FDX-1`
GF16 vs bfloat16 NMSE on D-1..D-6	▢ SPEC (golden vectors)	reference baselines in `docs/vectors/nmse/`; no silicon NMSE	`VC-NMSE-1..4`
Canonical 0x47C0 anchor (iverilog)	⊙ PRE-SILICON	passes on every push	`VC-ANCHOR-1`
Triple-Deck on φ-anchor	—	FBB at SYNTH; RBB and CAP_BOOST are planned-only	`VC-DECK-1..3`

The 22FDX band is sourced from TOPS_W_22FDX_PROJECTION.md, assumes Triple-Deck deployed in full, and remains band-only — a single point estimate is an R5 violation. Only FBB of the Triple-Deck is in RTL on this chip — see TRIPLE_DECK_STATUS.md and the state-machine spec docs/TRIPLE_DECKER_STATE_MACHINE.md.

The SKY130A demonstrator validates architecture, not absolute silicon performance.

Green AI Alignment

Ternary {−1, 0, +1} — ~10× energy/op vs FP16 at equivalent accuracy
0 DSP / 0 * — R-SI-1 RTL constraint eliminates multiplier switching energy
Edge inference — no datacenter transit, no PUE overhead
Open-source RTL — reproducible silicon eliminates duplicated tape-out waste

The Bazaar, not the Cathedral

"Many heads are inevitably better than one." — Eric S. Raymond, The Cathedral and the Bazaar (1997)

This repository is open under Apache-2.0 with no field-of-endeavor restriction. Fork it. Improve it. Build with it.

References

DOI: 10.5281/zenodo.19227877
PhD chapter: flos_70.tex — Ch. 36 TRI-1 Triad
CLARA proposal: TRI_NET_DARPA_CLARA_PROPOSAL.md

License: Apache-2.0 (see LICENSE)

Anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877

🔗 TRI-NET Cross-References

Component	Repository	Tiles	CLARA Gaps
φ-anchor	tt-trinity-phi (this repo)	1×1	1/10
e-engine	tt-trinity-euler	8×2	10/10
γ-surface	tt-trinity-gamma	8×4	10/10

All three dies emit the same canonical 0x47C0 on power-up (TG-TRIAD-X cross-die anchor).

Name		Name	Last commit message	Last commit date
Latest commit History 89 Commits
.github		.github
.trinity/seals		.trinity/seals
conformance		conformance
coq		coq
docs		docs
examples		examples
rtl_gen		rtl_gen
scripts		scripts
specs		specs
src		src
test		test
trios-coq		trios-coq
.gds_trigger		.gds_trigger
.gitignore		.gitignore
.zenodo.json		.zenodo.json
BENCHMARKS.md		BENCHMARKS.md
CHANGELOG.md		CHANGELOG.md
CLARA_TRACEABILITY.md		CLARA_TRACEABILITY.md
COMPETITORS.md		COMPETITORS.md
D2D_PROTOCOL.md		D2D_PROTOCOL.md
GF16_BFLOAT16_NMSE.md		GF16_BFLOAT16_NMSE.md
LICENSE		LICENSE
LINEUP.md		LINEUP.md
README.md		README.md
README_ORIGINAL.md		README_ORIGINAL.md
STATUS.md		STATUS.md
TOPS_W_22FDX_PROJECTION.md		TOPS_W_22FDX_PROJECTION.md
TRIPLE_DECK_STATUS.md		TRIPLE_DECK_STATUS.md
TRI_NET_API.md		TRI_NET_API.md
WHITEPAPER.md		WHITEPAPER.md
info.yaml		info.yaml

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TRI-1 Phi — Trinity φ-anchor (Canonical Seed + Lucas POST)

TL;DR

TRI-NET Positioning

Φ Identity Layer — Root of Trust

Cross-Die Anchor 0x47C0 — Theorem 36.1

Sibling Chips

TRI-NET vs. Alternatives — What Others Cannot Offer

Verification & Reproducibility

Claim status legend

Verification assets shipped today

Reproduce the spec gate locally

Zenodo / DOI status

Table of Contents

Quick Start

Prerequisites

Simulation

GDS Synthesis

What is φ-anchor?

Sacred Formula

Architecture

Single-Tile Structure

Enhanced Modules (v2)

Lucas POST

Algorithm

By Binet's Formula

Sacred ROMs

Sacred Constants ROM (75 cells)

Crown47 ROM (100 cells)

Build & Test

Local Simulation

GDS Synthesis

Pin Mapping

POST Status Byte (post_done=1, load_mode=0)

⚡ Performance Benchmarks

Throughput

Latency

Area (SKY130A)

Power (SKY130A @50MHz)

v1.0.0 Performance Impact

Development Guide

R-SI Compliance Rules

Adding Constants to Sacred ROM

Verifying Lucas POST

Contributing

Code Review Checklist

Troubleshooting

Canonical Test Failure

GDS DRC Errors

POST Failure

Competitive Analysis

No Competitor Has Native Ternary MAC

🏆 Competitive Differentiators

Green AI Manifesto

Honest Performance Disclosure (R5-HONEST)

Green AI Alignment

The Bazaar, not the Cathedral

References

🔗 TRI-NET Cross-References

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