Pinned Loading

1. ALU_simALU_simPublic

   Basic ALU simulator in HCS12 assembly.

   Assembly

2. bodebodePublic

   Bode plot generator for continuous LTI transfer functions.

   Python

3. DRAMCDRAMCPublic

   Behavioral architecture of a read/write cycle controller for a DRAM chip.

   VHDL 1

4. SDPMSDPMPublic

   Serial data processing module design/implementation using VHDL.

   Tcl

5. SN74ALS561ASN74ALS561APublic

   Behavioral architecture of a TI SN74ALS561A chip.

   Tcl

6. I82C55AI82C55APublic

   Parallel I/O interface module design/implementation using VHDL.

   VHDL