LibreLane

ASIC implementation flow infrastructure, successor to OpenLane

Python 525Apache-2.0 98 154 (4 issues need help) 10 Updated Aug 28, 2026

LibreLane Continuous Integration Designs

Verilog 6 3 1 0 Updated Aug 28, 2026

Repository to store metric results for LibreLane

0 4 0 0 Updated Aug 24, 2026

"Unit" tests for the LibreLane included step library

Verilog 1Apache-2.0 3 0 0 Updated Jul 10, 2026

Sources for the LibreLane Website

HTML 0 0 0 0 Updated Oct 1, 2025

Python wrapper around Yosys's `libparse` module

C++ 0Apache-2.0 6 0 0 Updated Aug 30, 2025

Collection of hardened layouts to verify LibreLane signoff results

1 0 0 0 Updated Jun 11, 2025

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