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1. FazyRVFazyRVPublic

   A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

   SystemVerilog 122 8

2. FazyRV-ExoTinyFazyRV-ExoTinyPublic

   Assembly 3 2

3. tt06-FazyRV-ExoTinytt06-FazyRV-ExoTinyPublic

   SystemVerilog 6

4. RV32I_SC_LogisimRV32I_SC_LogisimPublic

   A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

   Verilog 27 4

5. logIPlogIPPublic

   Logic Analyzer IP Core

   SystemVerilog 7 1

6. SimIOSimIOPublic

   SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

   Python 11