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FPGA IP core for Embedded MultiMediaCard (eMMC) interface controller.
Overview
Embedded Multi-Media Card (eMMC) is a type of non-volatile storage solution widely used in mobile devices, automotive systems, and embedded applications. It integrates NAND flash memory and a flash memory controller into a single package, providing a compact, cost-effective, and standardized storage interface.
The Lattice eMMC Controller IP is a soft IP block that implements the host-side JEDEC eMMC protocol, bridging an SoC's system bus to an external eMMC device over a 1/4/8-bit MMC interface. It manages the entire transaction lifecycle—command and response sequencing and data transfers. The IP provides memory-mapped control and status registers on standard APB interface, and AXI4 Manager interface for data transfer.
Features
JEDEC JESD84-B51A standard support
Data IO width: x1, x4, x8 support
AMBA AXI4 Manager bus interface for data transfer
AMBA APB bus interface for CSR access
eMMC clock frequencies up to 52 MHz, Single Data Rate
Programmable clock divider
Internal FIFO for data buffering (configurable depth)
Interrupt support
Optional IO primitive integration
Limitations / Not Yet Implemented
Higher data rate as well as DDR mode is currently not supported and may be added in the future.
Feature
Status
Description
DDR Mode
Not Implemented
Double Data Rate transfers
HS200
Not Implemented
High Speed 200 MB/s mode
HS400
Not Implemented
High Speed 400 MB/s mode
Boot Mode
Not Implemented
eMMC boot partition access
Current Maximum Speed: 52 MB/s (High Speed SDR mode)
RSP_DAT0-4 - Response Data Registers (Offset: 0x108-0x118)
Register
Offset
Description
RSP_DAT0
0x108
[5:0] Command index from response
RSP_DAT1
0x10C
Response bits [31:0]
RSP_DAT2
0x110
Response bits [63:32]
RSP_DAT3
0x114
Response bits [95:64]
RSP_DAT4
0x118
Response bits [127:96]
For R2 (136-bit) responses, all RSP_DAT registers contain valid data. For shorter responses (R1, R3, etc.), only RSP_DAT0 and RSP_DAT1 are relevant.
Programming Sequence
Initialization
De-assert reset (rst_n_i = 1) and wait at least 4 clock cycles
Configure clock divider in CFG0 for ~400 KHz initial clock
Set IO mode to Open-Drain (pp1_od0 = 0) and x1 width (io_width = 0)
Assert emmc_rst_n_o via SOFT_RST if needed
Send CMD0 (GO_IDLE_STATE) to reset the eMMC device
Send CMD1 (SEND_OP_COND) repeatedly until device is ready
Send CMD2 (ALL_SEND_CID) to get device CID
Send CMD3 (SET_RELATIVE_ADDR) to assign RCA
Sending Commands
Write command argument to CTRL1 (cmd_arg)
Configure CTRL0 if data transfer is needed (num_blocks, block_len)
Configure CTRL2 with command index and response type
Write 1 to cmd_start bit in CTRL2 to trigger command
Wait for cmd_done interrupt or poll INFO_STS[0] for busy status
Read response from RSP_DAT registers if applicable
Check INT_STS for any errors
Data Read Operation
Configure SRC_DST_ADDR with destination memory address
Set CTRL0: num_blocks and block_len
Send CMD17 (READ_SINGLE_BLOCK) or CMD18 (READ_MULTIPLE_BLOCK)
Wait for cmd_done interrupt
Data is automatically transferred via AXI4 to the configured address
Data Write Operation
Configure SRC_DST_ADDR with source memory address
Set CTRL0: num_blocks and block_len
Send CMD24 (WRITE_BLOCK) or CMD25 (WRITE_MULTIPLE_BLOCK)
Wait for cmd_done interrupt
Data is automatically transferred via AXI4 from the configured address
Switching to High Speed Mode
Complete initialization sequence
Send CMD6 (SWITCH) to set HS_TIMING in EXT_CSD
Update CFG0 clock divider for higher frequency (up to 52 MHz)
Set IO mode to Push-Pull (pp1_od0 = 1)
Optionally switch to x4 or x8 bus width via CMD6
Clocking
The eMMC Controller IP has a single input clock operating at up to 200 MHz. The IP generates the eMMC clock using internal clock divider. The eMMC clock frequency depends on the divider setting (clk_div):
For example, if the input clock is 200 MHz and the divider setting is 2, then the eMMC clock frequency is 50 MHz.
Reset
The eMMC Controller IP provides:
Hardware Reset (rst_n_i) - Asynchronous active-low reset for the entire IP including CSR. Minimum pulse width is one clock cycle.
IP Core Reset - Soft reset that resets the eMMC Controller logic except the CSR block
eMMC Target Reset - Resets the target device through emmc_rst_n_o
After de-asserting reset, wait for at least four clock cycles before starting any transaction.
Directory Structure
emmc_controller/
├── rtl/ # RTL source files (12 files)
├── testbench/ # Testbench files
├── sim/ # Simulation scripts
├── doc/ # Documentation (introduction.html)
├── driver/ # C driver files
├── plugin/ # Tool plugins
├── example_design/ # Example Propel SoC project
├── constraints/ # IP level constraints
├── scripts/ # Release and utility scripts
├── hooks/ # Git hooks
├── metadata.xml # IP metadata
├── settings.xml # IP parameter settings
├── ports.xml # IP port definitions
├── rtl_params.xml # RTL parameters
├── bus_interface.xml # Bus interface definitions
├── memory_map.xml # Memory map definitions
├── address_space.xml # Address space definitions
├── IP Release Notes.md # Revision history
├── QUICKSTART.md # Getting started guide
└── README.md # This file
RTL Files
File
Description
lscc_emmc_controller.v
Top-level wrapper
emmc_top.v
Core controller top
emmc_csr.v
Control/Status registers (APB subordinate)
emmc_cmd_proc.v
Command processor
emmc_axi4_m.v
AXI4 manager interface
emmc_ahbl_m.v
AHB-Lite manager interface
emmc_apb_s.v
APB subordinate interface
emmc_fifo.v
Data FIFO
emmc_clkgen.v
Clock generator/divider
emmc_serdes.v
Serializer/Deserializer
emmc_serdes_top.v
SERDES top wrapper
emmc_iologic.v
IO logic primitives
IP Configuration Parameters
The following parameters are configurable through the Radiant IP Catalog GUI. Default values are shown in bold.
User Interface
Attribute
Values
Description
CSR Interface (Target)
APB
Main interface to configure and control the IP registers (informational).
Enable Full CSR Address Decoding
Checked, Unchecked
If enabled, register address is decoded using full 32-bit address. If disabled, only lower 10 bits are decoded. Disable for Propel-based designs where address space is automatically allocated.
Register Map: APB Base Address (32b Hex)
0x00000000 – 0xFFFFFC00
Starting address of register space (1 KiB aligned). Only editable when full address decoding is enabled.
Data Interface (Controller)
AXI4, AHBL
Interface used by IP to move data between eMMC device and system memory.
AXI4 Bus ID Width
1 – 12
Width of AXI4 transaction ID signals. Only visible when Data Interface is AXI4.
FIFO Depth
512, 1024, 2048, 4096, 8192
Depth of data interface FIFO in bytes. Options depend on maximum block size.
FIFO Implementation
LUT, EBR, HARD IP
FIFO memory implementation type. Available options depend on device family.
Capabilities
Attribute
Values
Description
Enable Double Transfer Rate
Unchecked
DDR mode support (not yet implemented, always disabled).
Max Number of Data Lanes
X1, X4, X8
Maximum data IO width. X1=1-bit, X4=4-bit, X8=8-bit bidirectional data pins.
Minimum Block Size Supported (Bytes)
256 – 16384, 512
Minimum block size in bytes. Affects internal counter and register width.
Maximum Block Size Supported (Bytes)
256 – 16384, 1024
Maximum block size in bytes. Affects internal counter and register width.
Default Block Size (Bytes)
512
Default block size (informational, calculated from min block size).
Maximum Number of Blocks in Single Transfer
3, 7, 15, 31, 63, ..., 65535
Maximum blocks per read/write command. Affects internal counter and register width.
eMMC Maximum Speed (MBps)
1 – 52
Maximum device speed in MB/s. Affects clock frequency range and divider width.
Clock Configuration
Attribute
Values
Description
System Clock Frequency (MHz)
2 – 200, 100
System clock (clk_i) frequency. Range depends on eMMC maximum speed.
Internal Clock Frequency (MHz)
(calculated)
Same as system clock frequency (informational).
Minimum eMMC Clock Frequency (KHz)
10 – 400
Minimum eMMC clock frequency for initialization. Affects clock divider width.
Default eMMC Clock Pulse Width
0 – varies, 125
Default clock divider value. 0=same as clk_i, 1=divide by 2, 2=divide by 4, etc.
Default eMMC Clock Frequency (MHz)
(calculated)
Calculated as clk_i/(2×pulse_width) or clk_i if pulse_width=0 (informational).
Default eMMC Clock Period (ns)
(calculated)
Calculated from default eMMC clock frequency (informational).
IO Primitive
Attribute
Values
Description
Include IO Primitive
Checked, Unchecked
When enabled, eMMC command and data pins are bidirectional IO at top level (emmc_cmd_io, emmc_dat_io). When disabled, tristate control signals are exposed as separate ports (emmc_cmd_i/o/oe, emmc_dat_i/o/oe).
RTL Parameters
These parameters are passed to the Verilog module and are derived from the GUI settings above.
Parameter
Type
Default
Description
DEVICE_FAMILY
string
(auto)
Target FPGA family (from device selection)
SIMULATION
int
0
Enable simulation mode
DATA_INTERFACE
string
"AXI4"
Data interface type ("AXI4" or "AHBL")
CSR_INTERFACE
string
"APB"
CSR interface type
CLKI_FREQ
real
100.0
System clock frequency (MHz)
MAX_NUMLANE
int
8
Maximum data lanes (1, 4, or 8)
DEF_BLOCK_SIZE
int
512
Default block size (bytes)
MIN_BLOCK_SIZE
int
512
Minimum block size (bytes)
MAX_BLOCK_SIZE
int
1024
Maximum block size (bytes)
MAX_NUM_BLOCK
int
32
Maximum blocks per transfer (gui_max_num_blk + 1)
FIFO_DEPTH
int
512
FIFO depth in bytes
MEM_IMPL
string
"HARD_IP"
Memory implementation ("HARD_IP", "EBR", "LUT")
AXI4_TID_WIDTH
int
1
AXI4 transaction ID width (1–12)
CLKDIV_WID
int
(calc)
Clock divider register width (calculated from clock settings)
SPI_SCKDIV
int
125
Default clock divider value
USE_CLKDIV1
int
(calc)
Enable divide-by-1 mode (1 if min divider is 0)
USE_IO_PRIMITIVE
int
1
Include internal IO primitives (0 or 1)
EN_DDR_MODE
int
0
Enable DDR mode (not implemented)
EN_FULLADDR_DECODE
int
0
Enable full 32-bit address decoding
REG_BASE_ADDR
32-bit
32'h00000000
Register block base address
TMR_WIDTH
int
8
Timeout timer width (bits)
Port Descriptions
System Clock and Reset
Signal
Direction
Description
clk_i
Input
System clock. Maximum frequency is 200 MHz.
rst_n_i
Input
Asynchronous active-low reset. Minimum pulse width is one clock cycle. After de-asserting reset, wait at least 4 clock cycles before starting any transaction.
eMMC Interface
Signal
Direction
Width
Description
emmc_clk_o
Output
1
eMMC output clock. Generated by the IP, synchronous to command and data transfers. Idle state is low.
emmc_rst_n_o
Output
1
Asynchronous active-low reset to eMMC device. Controlled by programmable register. Default state is high.
emmc_dat_ds_i
Input
1
Data strobe input from eMMC device (for HS400 mode - not yet implemented).
With Internal IO Primitives (USE_IO_PRIMITIVE=1):
Signal
Direction
Width
Description
emmc_cmd_io
Inout
1
Bidirectional command channel. Open-drain for initialization, push-pull for fast transfers. Default state is tri-stated (device pull-up makes it high).
emmc_dat_io
Inout
[MAX_NUMLANE-1:0]
Bidirectional data channels (DAT0-DAT7). Push-pull mode. Width depends on MAX_NUMLANE parameter (1, 4, or 8). Default state is tri-stated.
With External IO Primitives (USE_IO_PRIMITIVE=0):
Signal
Direction
Width
Description
emmc_cmd_i
Input
1
Command input from external IO buffer
emmc_cmd_o
Output
1
Command output to external IO buffer. Default state is high.
emmc_cmd_oe_o
Output
1
Active-high command output enable. Default state is low.
emmc_dat_i
Input
[MAX_NUMLANE-1:0]
Data input from external IO buffer
emmc_dat_o
Output
[MAX_NUMLANE-1:0]
Data output to external IO buffer. Default state is high.
emmc_dat_oe_o
Output
[MAX_NUMLANE-1:0]
Active-high data output enable. Default state is low.
Interrupt
Signal
Direction
Description
int_o
Output
Level-sensitive active-high interrupt. Asserts when any enabled interrupt status bit is set.
AXI4 Manager Interface (Data Transfer)
Write Address Channel:
Signal
Direction
Width
Description
m_axi4_awready_i
Input
1
Write address ready
m_axi4_awvalid_o
Output
1
Write address valid
m_axi4_awid_o
Output
[AXI4_TID_WIDTH-1:0]
Write transaction ID
m_axi4_awaddr_o
Output
32
Write address (DWORD aligned)
m_axi4_awlen_o
Output
8
Burst length
m_axi4_awsize_o
Output
3
Burst size (fixed: 2 = 4 bytes)
m_axi4_awburst_o
Output
2
Burst type (fixed: 1 = INCR)
m_axi4_awprot_o
Output
3
Protection (tied to 0)
Write Data Channel:
Signal
Direction
Width
Description
m_axi4_wready_i
Input
1
Write data ready
m_axi4_wvalid_o
Output
1
Write data valid
m_axi4_wdata_o
Output
32
Write data
m_axi4_wstrb_o
Output
4
Write strobes
m_axi4_wlast_o
Output
1
Last write data in burst
Write Response Channel:
Signal
Direction
Width
Description
m_axi4_bready_o
Output
1
Write response ready
m_axi4_bvalid_i
Input
1
Write response valid
m_axi4_bid_i
Input
[AXI4_TID_WIDTH-1:0]
Write response ID
m_axi4_bresp_i
Input
2
Write response status
Read Address Channel:
Signal
Direction
Width
Description
m_axi4_arready_i
Input
1
Read address ready
m_axi4_arvalid_o
Output
1
Read address valid
m_axi4_arid_o
Output
[AXI4_TID_WIDTH-1:0]
Read transaction ID
m_axi4_araddr_o
Output
32
Read address (DWORD aligned)
m_axi4_arlen_o
Output
8
Burst length
m_axi4_arsize_o
Output
3
Burst size (fixed: 2 = 4 bytes)
m_axi4_arburst_o
Output
2
Burst type (fixed: 1 = INCR)
m_axi4_arprot_o
Output
3
Protection (tied to 0)
Read Data Channel:
Signal
Direction
Width
Description
m_axi4_rready_o
Output
1
Read data ready
m_axi4_rvalid_i
Input
1
Read data valid
m_axi4_rid_i
Input
[AXI4_TID_WIDTH-1:0]
Read response ID
m_axi4_rdata_i
Input
32
Read data
m_axi4_rresp_i
Input
2
Read response status
m_axi4_rlast_i
Input
1
Last read data in burst
AHB-Lite Manager Interface (Alternative Data Transfer)
Signal
Direction
Width
Description
m_ahbl_hsel_o
Output
1
AHB select
m_ahbl_haddr_o
Output
32
Address
m_ahbl_htrans_o
Output
2
Transfer type
m_ahbl_hwrite_o
Output
1
Write enable
m_ahbl_hsize_o
Output
3
Transfer size
m_ahbl_hburst_o
Output
3
Burst type
m_ahbl_hprot_o
Output
4
Protection
m_ahbl_hmastlock_o
Output
1
Locked transfer
m_ahbl_hwdata_o
Output
32
Write data
m_ahbl_hready_i
Input
1
Transfer done
m_ahbl_hresp_i
Input
1
Transfer response
m_ahbl_hrdata_i
Input
32
Read data
Note: AHB-Lite interface is available in RTL but not fully validated.
APB Subordinate Interface (CSR Access)
Signal
Direction
Width
Description
s_apb_psel_i
Input
1
APB select. Indicates target is selected for data transfer.
s_apb_penable_i
Input
1
APB enable. Indicates second cycle of APB transfer.