Add tiled MinMax MaxSim kernels

[juchen-ms (partychen)]

Summary

Adds a prepared MaxSim matrix kernel for MinMax8 queries against packed MinMax4 documents.

• packs each query once; query packing is excluded from per-document timing
• reads packed MinMax4 nibbles directly without a temporary unpacked document matrix
• preserves Driver -> PanelKernel -> MicroKernel
• fuses integer accumulation, MinMax compensation, and MaxSim reduction
• dispatches Scalar, x86-64 V3/V4, and ARM64 Neon through MaxSimIsa

Kernels

ISA	MR x NR	A packing	B expansion and dot product
Scalar	8 x 6	Row-major	Portable scalar loop
x86-64 V3	16 x 8	Grouped-4	AVX2 expansion + maddubs + madd
x86-64 V4	16 x 8	Grouped-8	BMI2 pdep_u64 + 512-bit VNNI
ARM64 Neon	8 x 8	Grouped-4	Scalar expansion + UDOT

V4 processes eight dimensions per step. Each pdep_u64 expands four packed MinMax4 bytes, VNNI accumulates two four-byte groups per query row, and adjacent accumulator lanes are combined before compensation.

The micro-kernel enters the selected target-feature context through run_inline. This is required for LLVM to emit direct vpdpbusd instructions instead of calling intrinsic shims from the contraction loop.

API

let kernel = build_minmax_max_sim(MaxSimIsa::Auto, query_minmax8,BoxErase)?;letmut scores = vec![0.0; kernel.nrows()];
kernel.compute_max_sim(doc_minmax4,&mut scores)?;

Performance

Workload: 1,000 documents, 16 query vectors x 16 document vectors x 250 dimensions. Query packing is performed once and excluded. All implementations produced identical results.

Platform	Existing Auto	Scalar	V3	V4	Neon
Intel Xeon Platinum 8370C	11.25 us/doc	7.66 us/doc	1.43 us/doc	0.53 us/doc	-
Snapdragon X Elite X1E80100	18.12 us/doc	2.33 us/doc	-	-	1.20 us/doc

Optimized path	Speedup vs Existing
x86-64 V3	7.87x
x86-64 V4	21.2x
ARM64 Neon	15.1x

On x86-64, Grouped-8 V4 is approximately 32% faster than the best Grouped-4 V4 variant. V3 retains AVX2 nibble expansion because it is within about 2% of BMI2 on this Intel CPU while avoiding slow pdep implementations on older AMD CPUs supported by V3.

Validation

cargo test -p diskann-quantization --release --lib minmax::multi::factory::tests
cargo clippy -p diskann-quantization --all-targets -- -D warnings
cargo check -p diskann-quantization --target aarch64-pc-windows-msvc

Scalar, V3, V4, Neon, and Auto match the existing MinMax8 x MinMax4 implementation across tested dimensions, row counts, and panel tails. Generated assembly contains direct vpdpbusd on V4 and direct udot on ARM64 Neon.