`<atomic>`: With `_STD_ATOMIC_ALWAYS_USE_CMPXCHG16B` defined to `1`, `atomic_ref<16 bytes>` does not report `is_lock_free` and `is_always_lock_free` correctly

[AlexGuteniev]

With _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B defined to 1 on x64, atomic_ref<16 bytes> reports is_lock_free and is_always_lock_free as both false. It should be both true.

[StephanTLavavej]

Thanks for noticing this bug. It's definitely a problem for ARM64, where this mode is always active:

STL/stl/inc/yvals.h

Lines 316 to 330 in d6efe94

	#ifndef _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B
	#if _STL_WIN32_WINNT >= _STL_WIN32_WINNT_WINBLUE && defined(_WIN64)
	#define _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B 1
	#else // ^^^ modern 64-bit / less modern or 32-bit vvv
	#define _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B 0
	#endif // _STL_WIN32_WINNT >= _STL_WIN32_WINNT_WINBLUE && defined(_WIN64)
	#endif // !defined(_STD_ATOMIC_ALWAYS_USE_CMPXCHG16B)
	#if _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 0 && defined(_M_ARM64)
	#error ARM64 requires _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B to be 1.
	#endif // _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 0 && defined(_M_ARM64)
	#if _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1 && !defined(_WIN64)
	#error _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1 requires 64-bit.
	#endif // _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1 && !defined(_WIN64)

At first I thought that is_lock_free() might be correct, but the code that checks _ATOMIC_HAS_DCAS and __std_atomic_has_cmpxchg16b() is just completely disabled, which is super wrong for ARM64 too:

STL/stl/inc/atomic

Lines 2169 to 2184 in d6efe94

	#if 1 // TRANSITION, ABI
	_NODISCARD bool is_lock_free() const volatile noexcept {
	constexpr bool _Result = sizeof(_Ty) <= 8 && (sizeof(_Ty) & sizeof(_Ty) - 1) == 0;
	return _Result;
	}
	#else // ^^^ don't break ABI / break ABI vvv
	_NODISCARD bool is_lock_free() const volatile noexcept {
	#if _ATOMIC_HAS_DCAS
	return sizeof(_Ty) <= 2 * sizeof(void*);
	#else // ^^^ _ATOMIC_HAS_DCAS / !_ATOMIC_HAS_DCAS vvv
	return sizeof(_Ty) <= sizeof(void*) || (sizeof(_Ty) <= 2 * sizeof(void*) && __std_atomic_has_cmpxchg16b());
	#endif // _ATOMIC_HAS_DCAS
	}
	#endif // ^^^ break ABI ^^^

We definitely need to fix this as it impacts ARM64. It would be nice to get rid of this mode and always use the new instruction for x64, but it's probably not possible to do that at this time. (We know for a fact that we must continue supporting SSE2-only processors that lack SSE4.2; cmpxchg16b is different but IIRC support for it appeared around the same time.)