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Merged
monoid merged 25 commits into from
Apr 11, 2026
Merged

harm: Applying relocations #52

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a8e48de
harm: refactor relocations
monoid Feb 21, 2026
f87cf43
harm: Applying relocations
monoid Feb 21, 2026
86e0805
Claude's tests
monoid Mar 6, 2026
eb59cc4
mov relocations
monoid Mar 6, 2026
efd81d8
Claude's tests 2
monoid Mar 7, 2026
6625179
fix memory Err values
monoid Mar 8, 2026
6a3e4ad
Fixing adrp relocations
monoid Mar 8, 2026
96013ee
Comments
monoid Mar 8, 2026
fe1a029
add_abs_lo_12_nc_reloc fix
monoid Mar 8, 2026
b0692e0
ldst_* relocations
monoid Mar 9, 2026
84471d1
Harmonize function names
monoid Mar 10, 2026
ae885a0
Misc
monoid Mar 14, 2026
da69d8a
Fix ABS32/ABS16/PREL32/PREL16 range check
monoid Mar 15, 2026
1d5d381
Rename symbols just like relocation's names
monoid Mar 15, 2026
3739b20
fix MOVW_SABS_*
monoid Mar 22, 2026
d37889b
MOVW_PREL
monoid Mar 15, 2026
446a864
MOVW_PREL tests by Claude
monoid Mar 22, 2026
673c9ee
PLT32
monoid Mar 28, 2026
c067f39
Misc
monoid Mar 28, 2026
3d824ba
Small refactorings
monoid Mar 29, 2026
2dd1f3b
More review improvements
monoid Apr 4, 2026
4568444
Common instruction patching function
monoid Apr 6, 2026
ce16373
Review and clippy fixes
monoid Apr 6, 2026
c03ca49
More review fixes
monoid Apr 11, 2026
2e3084a
More fixes
monoid Apr 11, 2026
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2 changes: 1 addition & 1 deletion aarchmrs-instructions/src/lib.rs
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Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down
18 changes: 9 additions & 9 deletions harm/src/instructions/control/branch_imm.rs
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Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
let zero = BranchOffset::default();

let code = B_only_branch_imm(zero.into());
let reloc = Rel64::Jump26(self.0);
let reloc = Rel64::jump26(self.0);

(code, Some(reloc))
}
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
let (cond, label_ref) = self.0;

let code = B_only_condbranch(zero.into(), cond.into());
let reloc = Rel64::CondBr19(label_ref);
let reloc = Rel64::cond_br19(label_ref);

(code, Some(reloc))
}
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
let zero = BranchOffset::default();

let code = BL_only_branch_imm(zero.into());
let reloc = Rel64::Call26(self.0);
let reloc = Rel64::call26(self.0);

(code, Some(reloc))
}
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
}
.to_code();

let reloc = Rel64::CondBr19(self.offset);
let reloc = Rel64::cond_br19(self.offset);

(code, Some(reloc))
}
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
}
.to_code();

let reloc = Rel64::CondBr19(self.offset);
let reloc = Rel64::cond_br19(self.offset);

(code, Some(reloc))
}
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

let (code, reloc) = inst.to_code_with_reloc();
assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
assert_eq!(reloc, Some(Rel64::CondBr19(label)));
assert_eq!(reloc, Some(Rel64::cond_br19(label)));
}

#[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

let (code, reloc) = inst.to_code_with_reloc();
assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
assert_eq!(reloc, Some(Rel64::CondBr19(label)));
assert_eq!(reloc, Some(Rel64::cond_br19(label)));
}

#[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

let (code, reloc) = inst.to_code_with_reloc();
assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
assert_eq!(reloc, Some(Rel64::CondBr19(label)));
assert_eq!(reloc, Some(Rel64::cond_br19(label)));
}

#[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

let (code, reloc) = inst.to_code_with_reloc();
assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
assert_eq!(reloc, Some(Rel64::CondBr19(label)));
assert_eq!(reloc, Some(Rel64::cond_br19(label)));
}
}
8 changes: 4 additions & 4 deletions harm/src/instructions/control/testbranch.rs
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Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
offset: TestBranchOffset::default(),
}
.to_code();
let rel = Rel64::TstBr14(self.offset.clone());
let rel = Rel64::tst_br14(self.offset.clone());
(code, Some(rel))
}
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
offset: TestBranchOffset::default(),
}
.to_code();
let rel = Rel64::TstBr14(self.offset.clone());
let rel = Rel64::tst_br14(self.offset.clone());
(code, Some(rel))
}
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
};
let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
assert_eq!(rel, Some(Rel64::TstBr14(label)));
assert_eq!(rel, Some(Rel64::tst_br14(label)));
}

#[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
};
let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
assert_eq!(rel, Some(Rel64::TstBr14(label)));
assert_eq!(rel, Some(Rel64::tst_br14(label)));
}
}
44 changes: 22 additions & 22 deletions harm/src/instructions/dpimm/movewide/movewide_reloc.rs
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Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG0(self.0)
Rel64::movw_uabs_g0(self.0)
}
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG0Nc(self.0)
Rel64::movw_uabs_g0_nc(self.0)
}
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG0S(self.0)
Rel64::movw_sabs_g0(self.0)
}
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG1(self.0)
Rel64::movw_uabs_g1(self.0)
}
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG1Nc(self.0)
Rel64::movw_uabs_g1_nc(self.0)
}
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG1S(self.0)
Rel64::movw_sabs_g1(self.0)
}
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG2(self.0)
Rel64::movw_uabs_g2(self.0)
}
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG2Nc(self.0)
Rel64::movw_uabs_g2_nc(self.0)
}
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG2S(self.0)
Rel64::movw_sabs_g2(self.0)
}
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

#[inline]
fn get_relocation(&self) -> Rel64 {
Rel64::MovWAbsG3(self.0)
Rel64::movw_uabs_g3(self.0)
}
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
};
let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
}

#[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
};
let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
}

#[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
// Makes little sense, but gas accepts it.
let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
}

#[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
};
let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
}

#[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
};
let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
}

#[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
};
let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
}

#[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
};
let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
}

#[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
};
let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
}

#[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
};
let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
}

#[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
};
let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
}

#[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
// Makes little sense, but gas accepts it.
let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
}

#[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
};
let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
}
}
1 change: 1 addition & 0 deletions harm/src/instructions/ldst.rs
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Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down
4 changes: 2 additions & 2 deletions harm/src/instructions/ldst/ldr.rs
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Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
LDR,
RegOrZero64,
64,
crate::reloc::Rel64::LdPrelLo19
crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
Ldr,
MakeLdr,
LDR,
RegOrZero32,
32,
crate::reloc::Rel64::LdPrelLo19
crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
2 changes: 1 addition & 1 deletion harm/src/instructions/ldst/ldrsw.rs
View file
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Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
LDRSW,
RegOrZero64,
64,
crate::reloc::Rel64::LdPrelLo19
crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
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harm: Applying relocations by monoid · Pull Request #52 · monoid/harm · GitHub
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harm: Applying relocations#52

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 Merged

monoid
merged 25 commits into

from

Apr 11, 2026
 Merged


harm: Applying relocations
#52
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a8e48de

harm: refactor relocations


monoid Feb 21, 2026
f87cf43

harm: Applying relocations


monoid Feb 21, 2026
86e0805

Claude's tests


monoid Mar 6, 2026
eb59cc4

mov relocations


monoid Mar 6, 2026
efd81d8

Claude's tests 2


monoid Mar 7, 2026
6625179

fix memory Err values


monoid Mar 8, 2026
6a3e4ad

Fixing adrp relocations


monoid Mar 8, 2026
96013ee

Comments


monoid Mar 8, 2026
fe1a029

add_abs_lo_12_nc_reloc fix


monoid Mar 8, 2026
b0692e0

ldst_* relocations


monoid Mar 9, 2026
84471d1

Harmonize function names


monoid Mar 10, 2026
ae885a0

Misc


monoid Mar 14, 2026
da69d8a

Fix ABS32/ABS16/PREL32/PREL16 range check


monoid Mar 15, 2026
1d5d381

Rename symbols just like relocation's names


monoid Mar 15, 2026
3739b20

fix MOVW_SABS_*


monoid Mar 22, 2026
d37889b

MOVW_PREL


monoid Mar 15, 2026
446a864

MOVW_PREL tests by Claude


monoid Mar 22, 2026
673c9ee

PLT32


monoid Mar 28, 2026
c067f39

Misc


monoid Mar 28, 2026
3d824ba

Small refactorings


monoid Mar 29, 2026
2dd1f3b

More review improvements


monoid Apr 4, 2026
4568444

Common instruction patching function


monoid Apr 6, 2026
ce16373

Review and clippy fixes


monoid Apr 6, 2026
c03ca49

More review fixes


monoid Apr 11, 2026
2e3084a

More fixes


monoid Apr 11, 2026

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2 changes: 1 addition & 1 deletion
aarchmrs-instructions/src/lib.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down

18 changes: 9 additions & 9 deletions
harm/src/instructions/control/branch_imm.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
 let zero = BranchOffset::default();

 let code = B_only_branch_imm(zero.into());
 let reloc = Rel64::Jump26(self.0);
 let reloc = Rel64::jump26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
 let (cond, label_ref) = self.0;

 let code = B_only_condbranch(zero.into(), cond.into());
 let reloc = Rel64::CondBr19(label_ref);
 let reloc = Rel64::cond_br19(label_ref);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
 let zero = BranchOffset::default();

 let code = BL_only_branch_imm(zero.into());
 let reloc = Rel64::Call26(self.0);
 let reloc = Rel64::call26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }
}

8 changes: 4 additions & 4 deletions
harm/src/instructions/control/testbranch.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
 };
 let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }

 #[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
 };
 let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }
}

44 changes: 22 additions & 22 deletions
harm/src/instructions/dpimm/movewide/movewide_reloc.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0(self.0)
 Rel64::movw_uabs_g0(self.0)
 }
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0Nc(self.0)
 Rel64::movw_uabs_g0_nc(self.0)
 }
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0S(self.0)
 Rel64::movw_sabs_g0(self.0)
 }
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1(self.0)
 Rel64::movw_uabs_g1(self.0)
 }
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1Nc(self.0)
 Rel64::movw_uabs_g1_nc(self.0)
 }
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1S(self.0)
 Rel64::movw_sabs_g1(self.0)
 }
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2(self.0)
 Rel64::movw_uabs_g2(self.0)
 }
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2Nc(self.0)
 Rel64::movw_uabs_g2_nc(self.0)
 }
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2S(self.0)
 Rel64::movw_sabs_g2(self.0)
 }
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG3(self.0)
 Rel64::movw_uabs_g3(self.0)
 }
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
 };
 let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
 };
 let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
 };
 let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }

 #[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
 };
 let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
 }

 #[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
 };
 let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
 }

 #[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
 };
 let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
 }

 #[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
 };
 let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
 }

 #[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
 };
 let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
 };
 let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
 };
 let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }
}

1 change: 1 addition & 0 deletions
harm/src/instructions/ldst.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down

4 changes: 2 additions & 2 deletions
harm/src/instructions/ldst/ldr.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
 LDR,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
 Ldr,
 MakeLdr,
 LDR,
 RegOrZero32,
 32,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down

2 changes: 1 addition & 1 deletion
harm/src/instructions/ldst/ldrsw.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
 LDRSW,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
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harm: Applying relocations by monoid · Pull Request #52 · monoid/harm · GitHub
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 Merged

monoid
merged 25 commits into

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Apr 11, 2026
 Merged


harm: Applying relocations
#52
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a8e48de

harm: refactor relocations


monoid Feb 21, 2026
f87cf43

harm: Applying relocations


monoid Feb 21, 2026
86e0805

Claude's tests


monoid Mar 6, 2026
eb59cc4

mov relocations


monoid Mar 6, 2026
efd81d8

Claude's tests 2


monoid Mar 7, 2026
6625179

fix memory Err values


monoid Mar 8, 2026
6a3e4ad

Fixing adrp relocations


monoid Mar 8, 2026
96013ee

Comments


monoid Mar 8, 2026
fe1a029

add_abs_lo_12_nc_reloc fix


monoid Mar 8, 2026
b0692e0

ldst_* relocations


monoid Mar 9, 2026
84471d1

Harmonize function names


monoid Mar 10, 2026
ae885a0

Misc


monoid Mar 14, 2026
da69d8a

Fix ABS32/ABS16/PREL32/PREL16 range check


monoid Mar 15, 2026
1d5d381

Rename symbols just like relocation's names


monoid Mar 15, 2026
3739b20

fix MOVW_SABS_*


monoid Mar 22, 2026
d37889b

MOVW_PREL


monoid Mar 15, 2026
446a864

MOVW_PREL tests by Claude


monoid Mar 22, 2026
673c9ee

PLT32


monoid Mar 28, 2026
c067f39

Misc


monoid Mar 28, 2026
3d824ba

Small refactorings


monoid Mar 29, 2026
2dd1f3b

More review improvements


monoid Apr 4, 2026
4568444

Common instruction patching function


monoid Apr 6, 2026
ce16373

Review and clippy fixes


monoid Apr 6, 2026
c03ca49

More review fixes


monoid Apr 11, 2026
2e3084a

More fixes


monoid Apr 11, 2026

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2 changes: 1 addition & 1 deletion
aarchmrs-instructions/src/lib.rs

View file


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Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down

18 changes: 9 additions & 9 deletions
harm/src/instructions/control/branch_imm.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
 let zero = BranchOffset::default();

 let code = B_only_branch_imm(zero.into());
 let reloc = Rel64::Jump26(self.0);
 let reloc = Rel64::jump26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
 let (cond, label_ref) = self.0;

 let code = B_only_condbranch(zero.into(), cond.into());
 let reloc = Rel64::CondBr19(label_ref);
 let reloc = Rel64::cond_br19(label_ref);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
 let zero = BranchOffset::default();

 let code = BL_only_branch_imm(zero.into());
 let reloc = Rel64::Call26(self.0);
 let reloc = Rel64::call26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }
}

8 changes: 4 additions & 4 deletions
harm/src/instructions/control/testbranch.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
 };
 let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }

 #[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
 };
 let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }
}

44 changes: 22 additions & 22 deletions
harm/src/instructions/dpimm/movewide/movewide_reloc.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0(self.0)
 Rel64::movw_uabs_g0(self.0)
 }
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0Nc(self.0)
 Rel64::movw_uabs_g0_nc(self.0)
 }
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0S(self.0)
 Rel64::movw_sabs_g0(self.0)
 }
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1(self.0)
 Rel64::movw_uabs_g1(self.0)
 }
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1Nc(self.0)
 Rel64::movw_uabs_g1_nc(self.0)
 }
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1S(self.0)
 Rel64::movw_sabs_g1(self.0)
 }
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2(self.0)
 Rel64::movw_uabs_g2(self.0)
 }
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2Nc(self.0)
 Rel64::movw_uabs_g2_nc(self.0)
 }
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2S(self.0)
 Rel64::movw_sabs_g2(self.0)
 }
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG3(self.0)
 Rel64::movw_uabs_g3(self.0)
 }
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
 };
 let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
 };
 let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
 };
 let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }

 #[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
 };
 let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
 }

 #[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
 };
 let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
 }

 #[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
 };
 let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
 }

 #[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
 };
 let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
 }

 #[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
 };
 let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
 };
 let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
 };
 let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }
}

1 change: 1 addition & 0 deletions
harm/src/instructions/ldst.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down

4 changes: 2 additions & 2 deletions
harm/src/instructions/ldst/ldr.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
 LDR,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
 Ldr,
 MakeLdr,
 LDR,
 RegOrZero32,
 32,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down

2 changes: 1 addition & 1 deletion
harm/src/instructions/ldst/ldrsw.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
 LDRSW,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Highlight search terms from Google/DuckDuckGo/Bing referrer
(function() {
var ref = document.referrer;
var terms = [];
if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {
var url = new URL(ref);
var q = url.searchParams.get('q') || url.searchParams.get('p');
if (q) {
terms = q.split(/\s+/).filter(function(t) { return t.length > 2; });
}
}
if (terms.length === 0) return;
var style = document.createElement('style');
style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';
document.head.appendChild(style);
function highlight(node) {
if (node.nodeType === 3) { // text node
var text = node.textContent;
var found = false;
terms.forEach(function(term) {
var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\]\\]/g, '\\') + ')', 'gi');
if (regex.test(text)) {
found = true;
var frag = document.createDocumentFragment();
var parts = text.split(regex);
parts.forEach(function(part, i) {
if (i % 2 === 0) {
frag.appendChild(document.createTextNode(part));
} else {
var span = document.createElement('span');
span.className = 'userscript-highlight';
span.textContent = part;
frag.appendChild(span);
}
});
node.parentNode.replaceChild(frag, node);
}
});
} else if (node.nodeType === 1 && node.childNodes) { // element
var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];
if (!skipTags.includes(node.tagName)) {
Array.from(node.childNodes).forEach(highlight);
}
}
}
highlight(document.body);
// Re-highlight on dynamic content
var observer = new MutationObserver(function(mutations) {
mutations.forEach(function(m) {
m.addedNodes.forEach(function(node) {
if (node.nodeType === 1 || node.nodeType === 3) highlight(node);
});
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})();
}
} catch(__e) { console.warn('[Userscript:Highlight Search Terms]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '
harm: Applying relocations by monoid · Pull Request #52 · monoid/harm · GitHub
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harm: Applying relocations#52

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harm: Applying relocations
#52
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a8e48de

harm: refactor relocations


monoid Feb 21, 2026
f87cf43

harm: Applying relocations


monoid Feb 21, 2026
86e0805

Claude's tests


monoid Mar 6, 2026
eb59cc4

mov relocations


monoid Mar 6, 2026
efd81d8

Claude's tests 2


monoid Mar 7, 2026
6625179

fix memory Err values


monoid Mar 8, 2026
6a3e4ad

Fixing adrp relocations


monoid Mar 8, 2026
96013ee

Comments


monoid Mar 8, 2026
fe1a029

add_abs_lo_12_nc_reloc fix


monoid Mar 8, 2026
b0692e0

ldst_* relocations


monoid Mar 9, 2026
84471d1

Harmonize function names


monoid Mar 10, 2026
ae885a0

Misc


monoid Mar 14, 2026
da69d8a

Fix ABS32/ABS16/PREL32/PREL16 range check


monoid Mar 15, 2026
1d5d381

Rename symbols just like relocation's names


monoid Mar 15, 2026
3739b20

fix MOVW_SABS_*


monoid Mar 22, 2026
d37889b

MOVW_PREL


monoid Mar 15, 2026
446a864

MOVW_PREL tests by Claude


monoid Mar 22, 2026
673c9ee

PLT32


monoid Mar 28, 2026
c067f39

Misc


monoid Mar 28, 2026
3d824ba

Small refactorings


monoid Mar 29, 2026
2dd1f3b

More review improvements


monoid Apr 4, 2026
4568444

Common instruction patching function


monoid Apr 6, 2026
ce16373

Review and clippy fixes


monoid Apr 6, 2026
c03ca49

More review fixes


monoid Apr 11, 2026
2e3084a

More fixes


monoid Apr 11, 2026

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2 changes: 1 addition & 1 deletion
aarchmrs-instructions/src/lib.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down

18 changes: 9 additions & 9 deletions
harm/src/instructions/control/branch_imm.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
 let zero = BranchOffset::default();

 let code = B_only_branch_imm(zero.into());
 let reloc = Rel64::Jump26(self.0);
 let reloc = Rel64::jump26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
 let (cond, label_ref) = self.0;

 let code = B_only_condbranch(zero.into(), cond.into());
 let reloc = Rel64::CondBr19(label_ref);
 let reloc = Rel64::cond_br19(label_ref);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
 let zero = BranchOffset::default();

 let code = BL_only_branch_imm(zero.into());
 let reloc = Rel64::Call26(self.0);
 let reloc = Rel64::call26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }
}

8 changes: 4 additions & 4 deletions
harm/src/instructions/control/testbranch.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
 };
 let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }

 #[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
 };
 let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }
}

44 changes: 22 additions & 22 deletions
harm/src/instructions/dpimm/movewide/movewide_reloc.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0(self.0)
 Rel64::movw_uabs_g0(self.0)
 }
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0Nc(self.0)
 Rel64::movw_uabs_g0_nc(self.0)
 }
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0S(self.0)
 Rel64::movw_sabs_g0(self.0)
 }
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1(self.0)
 Rel64::movw_uabs_g1(self.0)
 }
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1Nc(self.0)
 Rel64::movw_uabs_g1_nc(self.0)
 }
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1S(self.0)
 Rel64::movw_sabs_g1(self.0)
 }
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2(self.0)
 Rel64::movw_uabs_g2(self.0)
 }
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2Nc(self.0)
 Rel64::movw_uabs_g2_nc(self.0)
 }
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2S(self.0)
 Rel64::movw_sabs_g2(self.0)
 }
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG3(self.0)
 Rel64::movw_uabs_g3(self.0)
 }
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
 };
 let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
 };
 let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
 };
 let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }

 #[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
 };
 let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
 }

 #[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
 };
 let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
 }

 #[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
 };
 let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
 }

 #[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
 };
 let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
 }

 #[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
 };
 let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
 };
 let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
 };
 let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }
}

1 change: 1 addition & 0 deletions
harm/src/instructions/ldst.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down

4 changes: 2 additions & 2 deletions
harm/src/instructions/ldst/ldr.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
 LDR,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
 Ldr,
 MakeLdr,
 LDR,
 RegOrZero32,
 32,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down

2 changes: 1 addition & 1 deletion
harm/src/instructions/ldst/ldrsw.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
 LDRSW,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
// Strip utm_, fbclid, gclid, etc. from all links on page
(function() {
var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',
'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',
'ref', 'ref_src', 'source', 'medium', 'campaign'];
function cleanUrl(url) {
try {
var u = new URL(url, window.location.origin);
var changed = false;
trackingParams.forEach(function(p) {
if (u.searchParams.has(p)) {
u.searchParams.delete(p);
changed = true;
}
});
return changed ? u.toString() : url;
} catch (e) {
return url;
}
}
function cleanLinks() {
document.querySelectorAll('a[href]').forEach(function(a) {
var clean = cleanUrl(a.href);
if (clean !== a.href) a.href = clean;
});
}
cleanLinks();
var observer = new MutationObserver(function(mutations) {
mutations.forEach(function(m) {
m.addedNodes.forEach(function(node) {
if (node.nodeType === 1) {
if (node.tagName === 'A') cleanLinks();
node.querySelectorAll('a[href]').forEach(function(a) {
var clean = cleanUrl(a.href);
if (clean !== a.href) a.href = clean;
});
}
});
});
});
observer.observe(document.body, { childList: true, subtree: true });
})();
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '
harm: Applying relocations by monoid · Pull Request #52 · monoid/harm · GitHub
Skip to content
harm: Applying relocations#52

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 Merged

monoid
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harm: Applying relocations
#52
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a8e48de

harm: refactor relocations


monoid Feb 21, 2026
f87cf43

harm: Applying relocations


monoid Feb 21, 2026
86e0805

Claude's tests


monoid Mar 6, 2026
eb59cc4

mov relocations


monoid Mar 6, 2026
efd81d8

Claude's tests 2


monoid Mar 7, 2026
6625179

fix memory Err values


monoid Mar 8, 2026
6a3e4ad

Fixing adrp relocations


monoid Mar 8, 2026
96013ee

Comments


monoid Mar 8, 2026
fe1a029

add_abs_lo_12_nc_reloc fix


monoid Mar 8, 2026
b0692e0

ldst_* relocations


monoid Mar 9, 2026
84471d1

Harmonize function names


monoid Mar 10, 2026
ae885a0

Misc


monoid Mar 14, 2026
da69d8a

Fix ABS32/ABS16/PREL32/PREL16 range check


monoid Mar 15, 2026
1d5d381

Rename symbols just like relocation's names


monoid Mar 15, 2026
3739b20

fix MOVW_SABS_*


monoid Mar 22, 2026
d37889b

MOVW_PREL


monoid Mar 15, 2026
446a864

MOVW_PREL tests by Claude


monoid Mar 22, 2026
673c9ee

PLT32


monoid Mar 28, 2026
c067f39

Misc


monoid Mar 28, 2026
3d824ba

Small refactorings


monoid Mar 29, 2026
2dd1f3b

More review improvements


monoid Apr 4, 2026
4568444

Common instruction patching function


monoid Apr 6, 2026
ce16373

Review and clippy fixes


monoid Apr 6, 2026
c03ca49

More review fixes


monoid Apr 11, 2026
2e3084a

More fixes


monoid Apr 11, 2026

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2 changes: 1 addition & 1 deletion
aarchmrs-instructions/src/lib.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down

18 changes: 9 additions & 9 deletions
harm/src/instructions/control/branch_imm.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
 let zero = BranchOffset::default();

 let code = B_only_branch_imm(zero.into());
 let reloc = Rel64::Jump26(self.0);
 let reloc = Rel64::jump26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
 let (cond, label_ref) = self.0;

 let code = B_only_condbranch(zero.into(), cond.into());
 let reloc = Rel64::CondBr19(label_ref);
 let reloc = Rel64::cond_br19(label_ref);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
 let zero = BranchOffset::default();

 let code = BL_only_branch_imm(zero.into());
 let reloc = Rel64::Call26(self.0);
 let reloc = Rel64::call26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }
}

8 changes: 4 additions & 4 deletions
harm/src/instructions/control/testbranch.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
 };
 let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }

 #[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
 };
 let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }
}

44 changes: 22 additions & 22 deletions
harm/src/instructions/dpimm/movewide/movewide_reloc.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0(self.0)
 Rel64::movw_uabs_g0(self.0)
 }
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0Nc(self.0)
 Rel64::movw_uabs_g0_nc(self.0)
 }
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0S(self.0)
 Rel64::movw_sabs_g0(self.0)
 }
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1(self.0)
 Rel64::movw_uabs_g1(self.0)
 }
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1Nc(self.0)
 Rel64::movw_uabs_g1_nc(self.0)
 }
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1S(self.0)
 Rel64::movw_sabs_g1(self.0)
 }
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2(self.0)
 Rel64::movw_uabs_g2(self.0)
 }
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2Nc(self.0)
 Rel64::movw_uabs_g2_nc(self.0)
 }
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2S(self.0)
 Rel64::movw_sabs_g2(self.0)
 }
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG3(self.0)
 Rel64::movw_uabs_g3(self.0)
 }
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
 };
 let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
 };
 let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
 };
 let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }

 #[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
 };
 let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
 }

 #[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
 };
 let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
 }

 #[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
 };
 let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
 }

 #[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
 };
 let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
 }

 #[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
 };
 let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
 };
 let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
 };
 let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }
}

1 change: 1 addition & 0 deletions
harm/src/instructions/ldst.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down

4 changes: 2 additions & 2 deletions
harm/src/instructions/ldst/ldr.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
 LDR,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
 Ldr,
 MakeLdr,
 LDR,
 RegOrZero32,
 32,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down

2 changes: 1 addition & 1 deletion
harm/src/instructions/ldst/ldrsw.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
 LDRSW,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
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var btn = document.querySelector('button[aria-label="Theater mode"], ytd-player #player button[title="Theater mode"]');
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(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '
harm: Applying relocations by monoid · Pull Request #52 · monoid/harm · GitHub
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 Merged

monoid
merged 25 commits into

from

Apr 11, 2026
 Merged


harm: Applying relocations
#52
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a8e48de

harm: refactor relocations


monoid Feb 21, 2026
f87cf43

harm: Applying relocations


monoid Feb 21, 2026
86e0805

Claude's tests


monoid Mar 6, 2026
eb59cc4

mov relocations


monoid Mar 6, 2026
efd81d8

Claude's tests 2


monoid Mar 7, 2026
6625179

fix memory Err values


monoid Mar 8, 2026
6a3e4ad

Fixing adrp relocations


monoid Mar 8, 2026
96013ee

Comments


monoid Mar 8, 2026
fe1a029

add_abs_lo_12_nc_reloc fix


monoid Mar 8, 2026
b0692e0

ldst_* relocations


monoid Mar 9, 2026
84471d1

Harmonize function names


monoid Mar 10, 2026
ae885a0

Misc


monoid Mar 14, 2026
da69d8a

Fix ABS32/ABS16/PREL32/PREL16 range check


monoid Mar 15, 2026
1d5d381

Rename symbols just like relocation's names


monoid Mar 15, 2026
3739b20

fix MOVW_SABS_*


monoid Mar 22, 2026
d37889b

MOVW_PREL


monoid Mar 15, 2026
446a864

MOVW_PREL tests by Claude


monoid Mar 22, 2026
673c9ee

PLT32


monoid Mar 28, 2026
c067f39

Misc


monoid Mar 28, 2026
3d824ba

Small refactorings


monoid Mar 29, 2026
2dd1f3b

More review improvements


monoid Apr 4, 2026
4568444

Common instruction patching function


monoid Apr 6, 2026
ce16373

Review and clippy fixes


monoid Apr 6, 2026
c03ca49

More review fixes


monoid Apr 11, 2026
2e3084a

More fixes


monoid Apr 11, 2026

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2 changes: 1 addition & 1 deletion
aarchmrs-instructions/src/lib.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down

18 changes: 9 additions & 9 deletions
harm/src/instructions/control/branch_imm.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
 let zero = BranchOffset::default();

 let code = B_only_branch_imm(zero.into());
 let reloc = Rel64::Jump26(self.0);
 let reloc = Rel64::jump26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
 let (cond, label_ref) = self.0;

 let code = B_only_condbranch(zero.into(), cond.into());
 let reloc = Rel64::CondBr19(label_ref);
 let reloc = Rel64::cond_br19(label_ref);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
 let zero = BranchOffset::default();

 let code = BL_only_branch_imm(zero.into());
 let reloc = Rel64::Call26(self.0);
 let reloc = Rel64::call26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }
}

8 changes: 4 additions & 4 deletions
harm/src/instructions/control/testbranch.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
 };
 let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }

 #[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
 };
 let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }
}

44 changes: 22 additions & 22 deletions
harm/src/instructions/dpimm/movewide/movewide_reloc.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0(self.0)
 Rel64::movw_uabs_g0(self.0)
 }
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0Nc(self.0)
 Rel64::movw_uabs_g0_nc(self.0)
 }
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0S(self.0)
 Rel64::movw_sabs_g0(self.0)
 }
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1(self.0)
 Rel64::movw_uabs_g1(self.0)
 }
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1Nc(self.0)
 Rel64::movw_uabs_g1_nc(self.0)
 }
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1S(self.0)
 Rel64::movw_sabs_g1(self.0)
 }
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2(self.0)
 Rel64::movw_uabs_g2(self.0)
 }
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2Nc(self.0)
 Rel64::movw_uabs_g2_nc(self.0)
 }
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2S(self.0)
 Rel64::movw_sabs_g2(self.0)
 }
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG3(self.0)
 Rel64::movw_uabs_g3(self.0)
 }
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
 };
 let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
 };
 let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
 };
 let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }

 #[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
 };
 let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
 }

 #[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
 };
 let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
 }

 #[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
 };
 let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
 }

 #[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
 };
 let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
 }

 #[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
 };
 let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
 };
 let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
 };
 let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }
}

1 change: 1 addition & 0 deletions
harm/src/instructions/ldst.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down

4 changes: 2 additions & 2 deletions
harm/src/instructions/ldst/ldr.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
 LDR,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
 Ldr,
 MakeLdr,
 LDR,
 RegOrZero32,
 32,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down

2 changes: 1 addition & 1 deletion
harm/src/instructions/ldst/ldrsw.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
 LDRSW,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
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if (el.style.position === 'fixed' || el.style.position === 'sticky' || getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {
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})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '
harm: Applying relocations by monoid · Pull Request #52 · monoid/harm · GitHub
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 Merged

monoid
merged 25 commits into

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Apr 11, 2026
 Merged


harm: Applying relocations
#52
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a8e48de

harm: refactor relocations


monoid Feb 21, 2026
f87cf43

harm: Applying relocations


monoid Feb 21, 2026
86e0805

Claude's tests


monoid Mar 6, 2026
eb59cc4

mov relocations


monoid Mar 6, 2026
efd81d8

Claude's tests 2


monoid Mar 7, 2026
6625179

fix memory Err values


monoid Mar 8, 2026
6a3e4ad

Fixing adrp relocations


monoid Mar 8, 2026
96013ee

Comments


monoid Mar 8, 2026
fe1a029

add_abs_lo_12_nc_reloc fix


monoid Mar 8, 2026
b0692e0

ldst_* relocations


monoid Mar 9, 2026
84471d1

Harmonize function names


monoid Mar 10, 2026
ae885a0

Misc


monoid Mar 14, 2026
da69d8a

Fix ABS32/ABS16/PREL32/PREL16 range check


monoid Mar 15, 2026
1d5d381

Rename symbols just like relocation's names


monoid Mar 15, 2026
3739b20

fix MOVW_SABS_*


monoid Mar 22, 2026
d37889b

MOVW_PREL


monoid Mar 15, 2026
446a864

MOVW_PREL tests by Claude


monoid Mar 22, 2026
673c9ee

PLT32


monoid Mar 28, 2026
c067f39

Misc


monoid Mar 28, 2026
3d824ba

Small refactorings


monoid Mar 29, 2026
2dd1f3b

More review improvements


monoid Apr 4, 2026
4568444

Common instruction patching function


monoid Apr 6, 2026
ce16373

Review and clippy fixes


monoid Apr 6, 2026
c03ca49

More review fixes


monoid Apr 11, 2026
2e3084a

More fixes


monoid Apr 11, 2026

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2 changes: 1 addition & 1 deletion
aarchmrs-instructions/src/lib.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down

18 changes: 9 additions & 9 deletions
harm/src/instructions/control/branch_imm.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
 let zero = BranchOffset::default();

 let code = B_only_branch_imm(zero.into());
 let reloc = Rel64::Jump26(self.0);
 let reloc = Rel64::jump26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
 let (cond, label_ref) = self.0;

 let code = B_only_condbranch(zero.into(), cond.into());
 let reloc = Rel64::CondBr19(label_ref);
 let reloc = Rel64::cond_br19(label_ref);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
 let zero = BranchOffset::default();

 let code = BL_only_branch_imm(zero.into());
 let reloc = Rel64::Call26(self.0);
 let reloc = Rel64::call26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }
}

8 changes: 4 additions & 4 deletions
harm/src/instructions/control/testbranch.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
 };
 let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }

 #[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
 };
 let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }
}

44 changes: 22 additions & 22 deletions
harm/src/instructions/dpimm/movewide/movewide_reloc.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0(self.0)
 Rel64::movw_uabs_g0(self.0)
 }
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0Nc(self.0)
 Rel64::movw_uabs_g0_nc(self.0)
 }
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0S(self.0)
 Rel64::movw_sabs_g0(self.0)
 }
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1(self.0)
 Rel64::movw_uabs_g1(self.0)
 }
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1Nc(self.0)
 Rel64::movw_uabs_g1_nc(self.0)
 }
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1S(self.0)
 Rel64::movw_sabs_g1(self.0)
 }
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2(self.0)
 Rel64::movw_uabs_g2(self.0)
 }
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2Nc(self.0)
 Rel64::movw_uabs_g2_nc(self.0)
 }
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2S(self.0)
 Rel64::movw_sabs_g2(self.0)
 }
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG3(self.0)
 Rel64::movw_uabs_g3(self.0)
 }
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
 };
 let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
 };
 let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
 };
 let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }

 #[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
 };
 let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
 }

 #[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
 };
 let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
 }

 #[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
 };
 let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
 }

 #[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
 };
 let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
 }

 #[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
 };
 let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
 };
 let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
 };
 let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }
}

1 change: 1 addition & 0 deletions
harm/src/instructions/ldst.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down

4 changes: 2 additions & 2 deletions
harm/src/instructions/ldst/ldr.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
 LDR,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
 Ldr,
 MakeLdr,
 LDR,
 RegOrZero32,
 32,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down

2 changes: 1 addition & 1 deletion
harm/src/instructions/ldst/ldrsw.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
 LDRSW,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
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harm: Applying relocations by monoid · Pull Request #52 · monoid/harm · GitHub
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 Merged

monoid
merged 25 commits into

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Apr 11, 2026
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harm: Applying relocations
#52
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a8e48de

harm: refactor relocations


monoid Feb 21, 2026
f87cf43

harm: Applying relocations


monoid Feb 21, 2026
86e0805

Claude's tests


monoid Mar 6, 2026
eb59cc4

mov relocations


monoid Mar 6, 2026
efd81d8

Claude's tests 2


monoid Mar 7, 2026
6625179

fix memory Err values


monoid Mar 8, 2026
6a3e4ad

Fixing adrp relocations


monoid Mar 8, 2026
96013ee

Comments


monoid Mar 8, 2026
fe1a029

add_abs_lo_12_nc_reloc fix


monoid Mar 8, 2026
b0692e0

ldst_* relocations


monoid Mar 9, 2026
84471d1

Harmonize function names


monoid Mar 10, 2026
ae885a0

Misc


monoid Mar 14, 2026
da69d8a

Fix ABS32/ABS16/PREL32/PREL16 range check


monoid Mar 15, 2026
1d5d381

Rename symbols just like relocation's names


monoid Mar 15, 2026
3739b20

fix MOVW_SABS_*


monoid Mar 22, 2026
d37889b

MOVW_PREL


monoid Mar 15, 2026
446a864

MOVW_PREL tests by Claude


monoid Mar 22, 2026
673c9ee

PLT32


monoid Mar 28, 2026
c067f39

Misc


monoid Mar 28, 2026
3d824ba

Small refactorings


monoid Mar 29, 2026
2dd1f3b

More review improvements


monoid Apr 4, 2026
4568444

Common instruction patching function


monoid Apr 6, 2026
ce16373

Review and clippy fixes


monoid Apr 6, 2026
c03ca49

More review fixes


monoid Apr 11, 2026
2e3084a

More fixes


monoid Apr 11, 2026

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2 changes: 1 addition & 1 deletion
aarchmrs-instructions/src/lib.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -15,7 +15,7 @@ instruction variant described in the dataset, a corresponding Rust function is
generated.

The source code of this crate is generated by tools at the same repository at
https://github.com/monoid/harm.
<https://github.com/monoid/harm>.

As with the original dataset, this code is licensed under BSD-3-Clause license.

Expand Down

18 changes: 9 additions & 9 deletions
harm/src/instructions/control/branch_imm.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -127,7 +127,7 @@ impl RelocatableInstruction for Branch<LabelRef> {
 let zero = BranchOffset::default();

 let code = B_only_branch_imm(zero.into());
 let reloc = Rel64::Jump26(self.0);
 let reloc = Rel64::jump26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -186,7 +186,7 @@ impl RelocatableInstruction for Branch<(BranchCond, LabelRef)> {
 let (cond, label_ref) = self.0;

 let code = B_only_condbranch(zero.into(), cond.into());
 let reloc = Rel64::CondBr19(label_ref);
 let reloc = Rel64::cond_br19(label_ref);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -254,7 +254,7 @@ impl RelocatableInstruction for BranchLink<LabelRef> {
 let zero = BranchOffset::default();

 let code = BL_only_branch_imm(zero.into());
 let reloc = Rel64::Call26(self.0);
 let reloc = Rel64::call26(self.0);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -394,7 +394,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero64, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -425,7 +425,7 @@ impl RelocatableInstruction for CompareBranch<RegOrZero32, LabelRef> {
 }
 .to_code();

 let reloc = Rel64::CondBr19(self.offset);
 let reloc = Rel64::cond_br19(self.offset);

 (code, Some(reloc))
 }
Expand DownExpand Up@@ -712,7 +712,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(X3, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -725,7 +725,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbz(W4, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -738,7 +738,7 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(X5, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }

 #[test]
Expand All@@ -751,6 +751,6 @@ mod tests {

 let (code, reloc) = inst.to_code_with_reloc();
 assert_eq!(code, cbnz(W6, CompareBranchOffset::default()).to_code());
 assert_eq!(reloc, Some(Rel64::CondBr19(label)));
 assert_eq!(reloc, Some(Rel64::cond_br19(label)));
 }
}

8 changes: 4 additions & 4 deletions
harm/src/instructions/control/testbranch.rs

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Original file line numberDiff line numberDiff line change
Expand Up@@ -128,7 +128,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero64, TestBranchBit64, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand All@@ -143,7 +143,7 @@ impl RelocatableInstruction for TestBranch<RegOrZero32, TestBranchBit32, LabelRe
 offset: TestBranchOffset::default(),
 }
 .to_code();
 let rel = Rel64::TstBr14(self.offset.clone());
 let rel = Rel64::tst_br14(self.offset.clone());
 (code, Some(rel))
 }
}
Expand DownExpand Up@@ -321,7 +321,7 @@ mod tests {
 };
 let (opcode, rel) = tbz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }

 #[test]
Expand All@@ -333,6 +333,6 @@ mod tests {
 };
 let (opcode, rel) = tbnz(X2, bit, label.clone()).to_code_with_reloc();
 assert_eq!(opcode, tbnz(X2, bit, TestBranchOffset::default()).to_code());
 assert_eq!(rel, Some(Rel64::TstBr14(label)));
 assert_eq!(rel, Some(Rel64::tst_br14(label)));
 }
}

44 changes: 22 additions & 22 deletions
harm/src/instructions/dpimm/movewide/movewide_reloc.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -164,7 +164,7 @@ impl MoveWideReloc64 for AbsG0 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0(self.0)
 Rel64::movw_uabs_g0(self.0)
 }
}

Expand All@@ -176,7 +176,7 @@ impl MoveWideReloc64 for AbsG0Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0Nc(self.0)
 Rel64::movw_uabs_g0_nc(self.0)
 }
}

Expand All@@ -188,7 +188,7 @@ impl MoveWideReloc64 for AbsG0S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG0S(self.0)
 Rel64::movw_sabs_g0(self.0)
 }
}

Expand All@@ -200,7 +200,7 @@ impl MoveWideReloc64 for AbsG1 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1(self.0)
 Rel64::movw_uabs_g1(self.0)
 }
}

Expand All@@ -212,7 +212,7 @@ impl MoveWideReloc64 for AbsG1Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1Nc(self.0)
 Rel64::movw_uabs_g1_nc(self.0)
 }
}

Expand All@@ -224,7 +224,7 @@ impl MoveWideReloc64 for AbsG1S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG1S(self.0)
 Rel64::movw_sabs_g1(self.0)
 }
}

Expand All@@ -236,7 +236,7 @@ impl MoveWideReloc64 for AbsG2 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2(self.0)
 Rel64::movw_uabs_g2(self.0)
 }
}

Expand All@@ -248,7 +248,7 @@ impl MoveWideReloc64 for AbsG2Nc {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2Nc(self.0)
 Rel64::movw_uabs_g2_nc(self.0)
 }
}

Expand All@@ -260,7 +260,7 @@ impl MoveWideReloc64 for AbsG2S {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG2S(self.0)
 Rel64::movw_sabs_g2(self.0)
 }
}

Expand All@@ -272,7 +272,7 @@ impl MoveWideReloc64 for AbsG3 {

 #[inline]
 fn get_relocation(&self) -> Rel64 {
 Rel64::MovWAbsG3(self.0)
 Rel64::movw_uabs_g3(self.0)
 }
}

Expand DownExpand Up@@ -414,7 +414,7 @@ mod tests {
 };
 let inst = movz(X1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -425,7 +425,7 @@ mod tests {
 };
 let inst = movk(X2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -437,7 +437,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(X3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(X3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -448,7 +448,7 @@ mod tests {
 };
 let inst = movk(X4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }

 #[test]
Expand All@@ -459,7 +459,7 @@ mod tests {
 };
 let inst = movz(X5, abs_g2(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X5, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2(label)));
 }

 #[test]
Expand All@@ -470,7 +470,7 @@ mod tests {
 };
 let inst = movz(X6, abs_g2_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(X6, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g2(label)));
 }

 #[test]
Expand All@@ -481,7 +481,7 @@ mod tests {
 };
 let inst = movk(X7, abs_g2_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X7, (0, 32)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG2Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g2_nc(label)));
 }

 #[test]
Expand All@@ -492,7 +492,7 @@ mod tests {
 };
 let inst = movk(X8, abs_g3(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(X8, (0, 48)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG3(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g3(label)));
 }

 #[test]
Expand All@@ -503,7 +503,7 @@ mod tests {
 };
 let inst = movz(W1, abs_g0(label)).to_code_with_reloc();
 assert_eq!(inst.0, movz(W1, (0, 0)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG0(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g0(label)));
 }

 #[test]
Expand All@@ -514,7 +514,7 @@ mod tests {
 };
 let inst = movk(W2, abs_g1(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W2, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1(label)));
 }

 #[test]
Expand All@@ -526,7 +526,7 @@ mod tests {
 // Makes little sense, but gas accepts it.
 let inst = movn(W3, abs_g1_s(label)).to_code_with_reloc();
 assert_eq!(inst.0, movn(W3, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1S(label)));
 assert_eq!(inst.1, Some(Rel64::movw_sabs_g1(label)));
 }

 #[test]
Expand All@@ -537,6 +537,6 @@ mod tests {
 };
 let inst = movk(W4, abs_g1_nc(label)).to_code_with_reloc();
 assert_eq!(inst.0, movk(W4, (0, 16)).unwrap().to_code());
 assert_eq!(inst.1, Some(Rel64::MovWAbsG1Nc(label)));
 assert_eq!(inst.1, Some(Rel64::movw_uabs_g1_nc(label)));
 }
}

1 change: 1 addition & 0 deletions
harm/src/instructions/ldst.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -67,6 +67,7 @@ pub type ScaledOffset8 = UBitValue<12, 0>;
pub type ScaledOffset16 = UBitValue<12, 1>;
pub type ScaledOffset32 = UBitValue<12, 2>;
pub type ScaledOffset64 = UBitValue<12, 3>;
pub type ScaledOffset128 = UBitValue<12, 4>;

pub type UnscaledOffset = SBitValue<9>;

Expand Down

4 changes: 2 additions & 2 deletions
harm/src/instructions/ldst/ldr.rs

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -171,15 +171,15 @@ define_pc_offset_rules!(
 LDR,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);
define_pc_offset_rules!(
 Ldr,
 MakeLdr,
 LDR,
 RegOrZero32,
 32,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down

2 changes: 1 addition & 1 deletion
harm/src/instructions/ldst/ldrsw.rs

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -163,7 +163,7 @@ define_pc_offset_rules!(
 LDRSW,
 RegOrZero64,
 64,
 crate::reloc::Rel64::LdPrelLo19
 crate::reloc::Rel64::ld_prel_lo19
);

//
Expand Down
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