Skip to content
View oshears's full-sized avatar
😎
😎

Block or report oshears

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
oshears/README.md

About Osaze Shears 😎

Hi! I am a research computer engineer at University of Southern California's (USC) Information Sciences Institute (ISI) in Arlington, VA. I am is passionate about many engineering and computational concepts including embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Applications that interest me range from interactive technologies (Virtual and Mixed Reality) to bioinformatics!

I maintain a list of my professionala experiences and projects at my main website: oshears.github.io.

In my free time I work on game development projects with other artists and devs to develop multiplayer, VR, and 3D games. Updates are posted to my studio website: OSGames.


FPGA-ASIC Projects 💻

My FPGA-ASIC design projects include the following:

Experienced Open-Source Projects 🧠

I have had experience working with the following open-source hardware development projects:

  • OpenFPGA: Used to create and analyze FPGA architectures and bitstreams for custom architectures.
  • BladeRF: An open-source software defined radio (SDR).
  • Project X-Ray: Reverse engineering Xilinx Series 7 bitstreams.
  • Embedded Scalable Platforms (ESP): Open-source NoC generator with an Arianne RISC-V CPU and FPGA emulation capability.
  • Xilinx FINN: A neural netork compiler for Xilinx FPGAs.
  • RapidWright: A Java-based placement and routing tool for Xilinx FPGAs.
  • CocoTB: A Python-based RTL verification framework using the Verilog programming interface (VPI).

Game Development Projects 🎮

My game development projects include:


Collaborations 🤝🏽

I am actively seeking opportunities to collaborate on game design projects related to 3D, multiplayer, and virtual reality! Feel free to reach out by emailing oyshears@gmail.com.


My Website 🌐

oshears.github.io


My YouTube Channel 🎥

https://www.youtube.com/@osazeshears

Pinned Loading

  1. BindsNET-Self-DocumentationBindsNET-Self-DocumentationPublic archive

    Documentation created while learning BindsNET SNN Framework

    Jupyter Notebook 7 1

  2. neuromorphic_asic_bridgeneuromorphic_asic_bridgePublic

    The HDL FPGA Module to Interact with the MICS Neuromorphic Reservoir Computing ASIC

    VHDL 3

  3. fpga_snn_modelsfpga_snn_modelsPublic archive

    A repository FPGA-friendly SNN models

    Python 38 6

  4. SNN-FPGA-ImplementationSNN-FPGA-ImplementationPublic archive

    SystemVerilog 21 1

  5. bladerf_dfr_acceleratorbladerf_dfr_acceleratorPublic

    A project to implement a delayed feedback reservoir on the bladeRF 2.0 micro software defined radio (SDR) FPGA.

    SystemVerilog 5 2

  6. hybrid_dfr_systemhybrid_dfr_systemPublic archive

    The FPGA design for MICS' Hybrid DFR System

    VHDL 4 1