Skip to content
View pallaviphunde2003's full-sized avatar
2 followers · 2 following

Achievements

Achievement: Pull Shark

Achievements

Achievement: Pull Shark

Block or report pallaviphunde2003

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
pallaviphunde2003/README.md

Pallavi Phunde ✿

RTL Design · Design Verification · FPGA · Hardware Design

Electronics & Telecommunication Engineer interested in building, verifying, and debugging digital systems.

Verilog · SystemVerilog · UVM · FPGA · Hardware Design · Python · Git · Linux

Currently exploring:
Advanced UVM · SVA · CDC · SoC Verification

Popular repositories Loading

  1. Robocon-PCB Robocon-PCBPublic

    HTML

  2. Uart UartPublic

    Uart Serial Communication protocol.

    Verilog

  3. calcx calcxPublic

    Forked from vicharak-in/calcx

    Verilog

  4. square_root square_rootPublic

    Forked from vicharak-in/square_root

    // rah communication protocol developed for cpu-fpga link for vaaman rtl part

    Verilog

  5. sync_fifo sync_fifoPublic

    Verification of sync_fifo

    SystemVerilog

  6. UART_Verification UART_VerificationPublic

    SystemVerilog