+-----------------------+
| HOW TO RUN SIMULATION |
+-----------------------+
There are two ways to run simulation: using chiseltest, the built-in testing
method for Chisel; or using Verilator (or some other verilog simulation tool)
to run simulation manually.
You will need sbt, the Scala build tool, to compile the code. Before
simulating, please edit config.scala to make sure flags are set properly. You
will need to place the machine code to run in hexadecimal format on a file
named "data.data" in the current working directory. Input is read from
"infile.data" under cwd, also in hexadecimal format. These files are
configurable from config.scala, under p.testModule.
To run simulation using chiseltest:
1. You need to have Verilator installed.
2. Set mode to "test" in config.scala.
3. Run the test using the command "sbt run".
To run simulation manually:
1. Set mode to "codegen" in config.scala and make sure codegen.module is
"new TestModule" (not "new Cpu").
2. Generate Verilog code using the command "sbt run".
3. Copy src/main/resources/testbench.v to the current directory.
4. Run the simulation tool using testbench.v as the top module. For example,
using Verilator, you can use the following commands to run simulation:
verilator testbench.v --binary --timing -j $(nproc) --threads $(nproc) -Wno-UNOPTTHREADS -O3
./obj_dir/Vtestbench
If you want to play with the code, it is recommended that you spin up a sbt
daemon by running "sbt" and type in "run" each time you modify the code,
instead of running "sbt run" each time, to take full advantage of incremental
compilation provided by sbt.
+----------------------+
| HOW TO RUN SYNTHESIS |
+----------------------+
1. Make sure Vivado is installed.
2. Create a new project in Vivado.
3. Set mode to "codegen" in config.scala and make sure codegen.module is
"new Cpu" (not "new TestModule").
4. Generate Verilog code using the command "sbt run".
5. Copy the Verilog files in src/main/resources EXCEPT testbench.v, and copy
Cpu.v generated in step 4, to the Vivado project you have just created.
6. Run synthesis in Vivado.
+---------------+
| TESTING NOTES |
+---------------+
Icarus Verilog is unable to simulate some patterns in the CPU design, so please
use Verilator.
+-----------+
| HCI NOTES |
+-----------+
Some modifications are made to the HCI to better accomodate debugging.
The 7-segment display is used to show the current program counter. You need to
press the left button (BTNL) to update the display (or else it flashes too
quickly that you won't be able to see anything.) There are two sources of PC
data, and switch SW1 is used to control which is shown. Turn off SW1 to show
the last PC committed by the reorder buffer; turn on to show the current PC
being fetched by the instruction fetch unit. In RV32, the address is 32-bit,
but the display could only show a 16-bit hexadecimal number. SW0 is used to
toggle which 16 bits are shown. Switch on to see the high 16 bits (which are
usually just zeroes), and switch off to see low 16 bits. The switches will not
trigger display updates; you need to press the left button after switching.
Note that the last committed PC is initialized to be 0xDEADBEEF.
The LEDs are used to show the status of some design units:
LD0 on --> debug break
LD1 on --> io buffer full
LD2 on --> store buffer full
LD3 on --> load buffer full
LD4 on --> reservation station (for ALU) full
LD5 on --> reorder buffer full
LD6 on --> load/store queue full
The central button (BTNC) is used as the reset button as usual.