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Design overview:facebook#102
| Grouping | Description | Intel PR | Meta PR | Notes |
|---|
| Independent preparatory changes | | | | |
| Shortened critical section | | facebook#132 | Performance improvement |
| Per-pool cache stats | | facebook#141 | Benchmarking stats improvement |
| Add value validation to cachebench | | facebook#131 | Benchmarking improvement |
| Alternative locking approach for item movement | #36 | | Performance improvement |
| File-mapped memory support in shared memory manager | | facebook#146 | Enables access to PMEM memory |
| Initial set of changes to config API | | facebook#138 | First mention of memory tiers, only one DRAM tier is allowed |
| Tiers enabling changes | | | | |
| Enable tiers in allocator | TBD | | The feature is complete on the Intel fork |
| Enable tiers in config API | TBD | | The feature is complete on the Intel fork |
| Enable multi-tier eviction | TBD | | The feature is complete on the Intel fork |
| Future work | | | | |
| Scalable eviction policy | TBD | | Partition 2Q into independent structures so they use separate locks per region |
| Background eviction thread | TBD | | Performance improvement |
Design overview:facebook#102