ACE SystemVerilog modules for cache coherent SoC design

This repository provides modules to implement cache coherence SoC's.

List of modules

Name	Description	Doc
`ace_ccu_top`	ACE interconnector, broadcasts snooping messages to the cache controllers and AXI transactions to the slave	Doc

The ACE repository is released under Solderpad v0.51 (SHL-0.51) see LICENSE

Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
doc		doc
include/ace		include/ace
scripts		scripts
src		src
test		test
.gitignore		.gitignore
Bender.yml		Bender.yml
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
ace.core		ace.core
src_files.yml		src_files.yml