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[ExecuTorch][WebGPU] Support byte-packed BOOL storage - #21663
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**Support exact byte-packed BOOL tensors** WebGPU storage and transfers require four-byte alignment while serialized `BOOL` tensors use one logical byte per element. The runtime now preserves exact `BOOL` dtype and logical byte counts while padding physical storage, uploads, and readback. Key changes: - Compare output — packs guarded tail lanes for arbitrary nonzero lengths. - `BOOL`-to-fp32 — decodes packed values numerically instead of reinterpreting bytes. - `_to_copy` routing — mirrors Vulkan exact-dtype conversion intent in `backends/vulkan/runtime/graph/ops/impl/View.cpp:183` while keeping `BOOL` separate from `INT8` and `UINT8`. - Generated sources — refresh WGSL registry output and drift digests. Logical tensor sizes and existing non-`BOOL` routes are unchanged. Co-authored-with: Claude Code. Differential Revision: [D114936143](https://our.internmc.facebook.com/intern/diff/D114936143/) ghstack-source-id: 411044625 Pull-Request: #21598
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21663
Note: Links to docs will display an error until the docs builds have been completed. ⏳ No Failures, 8 PendingAs of commit daad2d1 with merge base ad3a71f ( This comment was automatically generated by Dr. CI and updates every 15 minutes. |
**Exercise byte-packed BOOL tails through export and native execution** Manifest and export coverage now proves exact `BOOL` storage and numeric `BOOL`-to-fp32 conversion across word-aligned and tail lengths. The native driver preserves `BOOL` metadata and compares canonical raw 0/1 bytes rather than semantic truth values. Key changes: - Length coverage — exercises 1, 4, 5, and 67 elements. - Export assertions — keep the fp32 cast inside the delegate while `INT8` stays outside the `BOOL` route. - Native validation — checks direct inputs, comparison outputs, and raw tail bytes. This is coverage-only; runtime kernels are unchanged. Co-authored-with: Claude Code. Differential Revision: [D114936146](https://our.internmc.facebook.com/intern/diff/D114936146/) ghstack-source-id: 411044629 Pull-Request: #21599
**Add a buffer-only groups=1 Conv1d kernel for Voxtral encoder shapes** The WebGPU backend handled only K=1 pointwise and depthwise Conv1d, leaving non-transposed groups=1 K=3 encoder convolutions unsupported. **Before** - Groups=1 K>1 graphs had no valid WebGPU route. **After** - A direct NCL buffer kernel supports groups=1 convolution with stride, padding, dilation, and optional bias. Key changes: - `add_conv1d_node` — validates fp32 operands, geometry, shapes, and shader index ranges. - `conv1d.wgsl` — mirrors Vulkan output indexing in `backends/vulkan/runtime/graph/ops/glsl/conv1d.glsl:78`, stride/padding at `:86`, and the kernel FMA loop at `:108`. - Dispatch and resize hooks — fold x/y workgroups and recompute live parameters safely. - Generated sources — refresh WGSL headers, registry output, and drift digests. The route remains limited to non-transposed groups=1 fp32 convolution; existing pointwise and depthwise routes are unchanged. Co-authored-with: Claude Code. Differential Revision: [D114936145](https://our.internmc.facebook.com/intern/diff/D114936145/) ghstack-source-id: 411044636 Pull-Request: #21600
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This PR was created by the merge bot to help merge the original PR into the main branch.
ghstack PR number: #21598 by @JCNTH
^ Please use this as the source of truth for the PR details, comments, and reviews
ghstack PR base: https://github.com/pytorch/executorch/tree/gh/JCNTH/205/base
ghstack PR head: https://github.com/pytorch/executorch/tree/gh/JCNTH/205/head
Merge bot PR base: https://github.com/pytorch/executorch/tree/gh/JCNTH/204/orig
Merge bot PR head: https://github.com/pytorch/executorch/tree/gh/JCNTH/205/orig
Differential Revision: D114936143
@diff-train-skip-merge