Enable IPCB for Hamoa and Glymur

arch/arm64/boot/dts/qcom/Makefile

@@ -532,3 +532,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= talos-evk-camx.dtb
 dtb-$(CONFIG_ARCH_QCOM) += talos-staging.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM) += kodiak-staging.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += hamoa-staging.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= glymur-staging.dtbo

arch/arm64/boot/dts/qcom/glymur-staging.dtso

@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * Glymur staging overlay - add staging-specific device tree modifications here.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&soc {
+	ctcu@10001000 {
+ compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu";
+ reg = <0x0 0x10001000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ctcu_in0: endpoint {
+ remote-endpoint = <&etr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ctcu_in1: endpoint {
+ remote-endpoint = <&etr1_out>;
+ };
+ };
+ };
+	};
+
+	replicator@10046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x10046000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ qdss_rep_in: endpoint {
+ remote-endpoint = <&swao_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_rep_out0: endpoint {
+ remote-endpoint = <&etr_rep_in>;
+ };
+ };
+ };
+	};
+
+	tmc@10048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x10048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ iommus = <&apps_smmu 0x00e0 0x0000>;
+
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint = <&etr_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint = <&ctcu_in0>;
+ };
+ };
+ };
+	};
+
+	replicator@1004e000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1004e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_rep_in: endpoint {
+ remote-endpoint = <&qdss_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ etr_rep_out0: endpoint {
+ remote-endpoint = <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ etr_rep_out1: endpoint {
+ remote-endpoint = <&etr1_in>;
+ };
+ };
+ };
+	};
+
+	tmc@1004f000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x1004f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ iommus = <&apps_smmu 0x0100 0x0000>;
+
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr1_in: endpoint {
+ remote-endpoint = <&etr_rep_out1>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr1_out: endpoint {
+ remote-endpoint = <&ctcu_in1>;
+ };
+ };
+ };
+	};
+
+	tgu@11c02000 {
+ compatible = "qcom,tgu", "arm,primecell";
+ reg = <0x0 0x11c02000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+	};
+
+	replicator@11c06000 {
+ out-ports {
+ port@0 {
+ reg = <0>;
+
+ swao_rep_out0: endpoint {
+ remote-endpoint = <&qdss_rep_in>;
+ };
+ };
+ };
+	};
+
+	tgu@11c0e000 {
+ compatible = "qcom,tgu", "arm,primecell";
+ reg = <0x0 0x11c0e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+	};
+
+	tgu@11c0f000 {
+ compatible = "qcom,tgu", "arm,primecell";
+ reg = <0x0 0x11c0f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+	};
+
+	tgu@11c10000 {
+ compatible = "qcom,tgu", "arm,primecell";
+ reg = <0x0 0x11c10000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+	};
+};

arch/arm64/boot/dts/qcom/hamoa-staging.dtso

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * Hamoa staging overlay - add staging-specific device tree modifications here.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&soc {
+	tgu@10b0e000 {
+ compatible = "qcom,tgu", "arm,primecell";
+ reg = <0x0 0x10b0e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+	};
+
+	tgu@10b0f000 {
+ compatible = "qcom,tgu", "arm,primecell";
+ reg = <0x0 0x10b0f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+	};
+
+	tgu@10b10000 {
+ compatible = "qcom,tgu", "arm,primecell";
+ reg = <0x0 0x10b10000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+	};
+};