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FROMLIST: PCI: Add support for PCIe WAKE# interrupt - #788
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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818a439CompareMerge Check Failed: CR Not Eligible for Merge CR 4542930 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 4542930 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
qlijarvis
commented
Jul 6, 2026
PR #788 — validate-patchPR:#788
Final Summary
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qlijarvis
commented
Jul 6, 2026
PR #788 — checker-log-analyzerPR:#788
Detailed report: Full report
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qlijarvis
commented
Jul 8, 2026
🔨 Build Failure Analysis — PR #788PR:#788
VerdictBoth errors are introduced by this PR. The PR adds a new function 📎 Detailed analysis:Full report |
qlijarvis
commented
Jul 8, 2026
🔨 Build Failure Analysis — PR #788PR:#788
Verdict1 of 1 errors is introduced by this PR. The error occurs in both standard and RT kernel builds. 📎 Detailed analysis:Full report |
Salendarsingh Gaud (sgaud-quic)
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Please fix compliation issue
Add fwnode_gpiod_get() as a convenience wrapper around fwnode_gpiod_get_index() for the common case where only the first GPIO is required. This mirrors existing gpiod_get() and devm_gpiod_get() helpers and avoids open-coding index 0 at call sites. Suggested-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260511-wakeirq_support-v10-1-c10af9c9eb8c@oss.qualcomm.com/
According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2), two link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a hardware-only mechanism and is invisible to software (PCIe r7.0, Section 4.2.7.8.1). This change adds support for the WAKE# mechanism in the PCI core. According to the PCIe specification, multiple WAKE# signals can exist in a system or each component in the hierarchy could share a single WAKE# signal. In configurations involving a PCIe switch, each downstream port (DSP) of the switch may be connected to a separate WAKE# line, allowing each endpoint to signal WAKE# independently. From figure 5.4 in sec 5.3.3.2, WAKE# can also be terminated at the switch itself. Such topologies are typically not described in Device Tree, therefore it is out of scope for this series. To support this, the WAKE# should be described in the device tree node of the endpoint/bridge. If all endpoints share a single WAKE# line, then each endpoint node shall describe the same WAKE# signal or a single WAKE# in the Root Port node. In pci_device_add(), PCI framework will search for the WAKE# in device node. Once found, register for the wake IRQ through dev_pm_set_dedicated_wake_irq() associates a wakeup IRQ with a device and requests it, but the PM core keeps the IRQ disabled by default. The IRQ is enabled by the PM core, only when the device is permitted to wake the system, i.e. during system suspend and after runtime suspend, and only when device wakeup is enabled. If the same WAKE# GPIO is described in multiple device tree nodes, only the first device that successfully registers the wake IRQ will succeed, while subsequent registrations may fail. This limitation does not affect functional correctness, since WAKE# is only used to bring the link to D0, and endpoint-specific wakeup handling is resolved later through PME detection (PME_EN is set in suspend path by PCI core by default). When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() to bring the device back to an active power state, such as transitioning from D3cold to D0. Once the device is active and the link is usable, the endpoint may generate a PME, which is then handled by the PCI core through PME polling or the PCIe PME service driver to complete the wakeup of the endpoint. WAKE# is added in dts schema and merged based on below links. Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/ Link: devicetree-org/dt-schema#170 Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260624-wakeirq_support-v11-1-120fbfaebe59@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
818a439 to
f610fa9Compareziyuezhang-123
commented
Jul 15, 2026
Hi Salendar, the compliation is fixed |
qcomlnxci
commented
Jul 15, 2026
Test Matrix
|
ziyuezhang-123
commented
Aug 7, 2026
Hi Salendarsingh Gaud (@sgaud-quic) need your help to merge the PR |
qcomlnxci
commented
Aug 11, 2026
Test Matrix
|
qcomlnxci
commented
Aug 11, 2026
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788
VerdictNo compilation errors found. Both kernel builds (standard and RT) completed successfully. The workflow failure was caused by a network timeout when submitting test jobs to the LAVA server ( 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 Build Status: ✅ SUCCESSFULBoth the standard and RT kernel builds completed successfully with no compilation errors.
VerdictNo compilation errors were introduced by this PR. The workflow failure was caused by LAVA test job submission failure (infrastructure issue), not by build errors. The PR changes compile cleanly and do not break the kernel build. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 Build Status: ✅ PASSEDBoth kernel builds completed successfully:
Workflow Failure Root CauseThe workflow failed during the test submission phase, not during compilation. All test jobs (qcs6490-rb3gen2, hamoa-iot-evk, lemans-evk, monaco-evk, purwa-iot-evk, qcs615-ride, qcs8300-ride, qcs9100-ride-r3, qrb2210-rb1, shikra-iqs-evk) failed with: This is a test infrastructure issue, not a build or code issue introduced by the PR. VerdictNo compilation errors found. The PR introduces GPIO and PCIe WAKE# support changes that compiled cleanly. The workflow failure is due to LAVA test submission infrastructure problems, which are unrelated to the code changes in this PR. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 Build Status: ✅ SUCCESSBoth kernel builds (standard and RT) completed successfully with no compilation errors. Test Status: ❌ FAILED (Infrastructure Issue)All 10 LAVA test job submissions failed due to network connectivity timeout to
VerdictNo compilation errors were introduced by this PR. The workflow failure is due to infrastructure issues (LAVA server connectivity), not code problems. The PR changes are build-clean. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 Build Status: ✅ SUCCESSBoth kernel builds (default and RT) completed successfully with no compilation errors.
Workflow Failure Root CauseThe workflow was marked as failed due to a LAVA test submission timeout, not a build failure: This is a network/infrastructure issue with the LAVA test server, completely unrelated to the PR changes. Verdict0 compilation errors found. The PR introduces no build failures. The workflow failure is due to test infrastructure connectivity issues, not code problems. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788
VerdictThe kernel build completed successfully for both standard and RT configurations. The workflow failure was caused by LAVA test infrastructure timeout (unable to connect to lava-oss.qualcomm.com), not by compilation errors. Zero build errors were introduced by this PR. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 Build Status: ✅ SUCCESSBoth kernel builds (standard and RT) completed successfully with no compilation errors. Workflow Failure Root CauseThe workflow was marked as failed due to LAVA test submission timeouts, not build failures:
VerdictNo build errors were introduced by this PR. The kernel compiled successfully for both standard and RT configurations. The workflow failure is due to infrastructure issues (LAVA server connectivity timeout), not code problems. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 ✅ Build Status: SUCCESSBoth kernel builds completed successfully:
VerdictNo build failures detected. The workflow failure was caused by test infrastructure issues (LAVA job submission failures), not compilation errors. All code changes in this PR compiled cleanly. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 Build Status: ✅ SUCCESSFULBoth kernel builds (standard and RT) completed successfully with zero compilation errors.
Workflow Failure Root CauseThe workflow failed during the test submission phase, not during compilation. The failure occurred when attempting to submit LAVA test jobs to VerdictThis PR introduces ZERO compilation errors. The workflow failure is due to a network connectivity timeout when submitting test jobs to the LAVA infrastructure, which is unrelated to the code changes in this PR. The PR changes (adding PCIe WAKE# GPIO support) compiled cleanly on all targets. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 11, 2026
🔨 Build Failure Analysis — PR #788PR:#788 Build Status: ✅ SUCCESSBoth kernel builds completed successfully with no compilation errors.
Workflow Failure Root CauseThe GitHub Actions workflow reported failure status, but this was NOT due to compilation errors. The failure occurred during the test job submission phase: Error: Affected test jobs: All 10 device test submissions (qcs6490-rb3gen2, qrb2210-rb1, monaco-evk, lemans-evk, qcs615-ride, qcs8300-ride, qcs9100-ride-r3, shikra-iqs-evk, hamoa-iot-evk, purwa-iot-evk) Verdict0 compilation errors. The PR changes compile cleanly. The workflow failure is due to infrastructure issues (LAVA server connectivity timeout), not code problems introduced by this PR. 📎 Detailed analysis:Full report |
qcomlnxci
commented
Aug 13, 2026
Test Matrix
|
qcomlnxci
commented
Aug 13, 2026
qcomlnxci
commented
Aug 18, 2026
qcomlnxci
commented
Aug 18, 2026
Test Matrix
|
795bab7
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Change task cannot be moved to Dev Complete CR: 4542930 The change task for this CR cannot be automatically moved to Dev Complete due to the error above. Please resolve the issue mentioned in the error and manually change the change task status to Dev Complete in Orbit. |
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Change task cannot be moved to Dev Complete CR: 4542930 The change task for this CR cannot be automatically moved to Dev Complete due to the error above. Please resolve the issue mentioned in the error and manually change the change task status to Dev Complete in Orbit. |
qlijarvis
commented
Aug 21, 2026
LAVA Failed Case Triage SummaryPR: #788 Job 207668 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207668 Failed test cases in LAVA job 207668 (SoC: qcs9100-ride).
Job 207669 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207669 Failed test cases in LAVA job 207669 (SoC: qcs8300-ride).
Job 207670 | SoC purwa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207670 Failed test cases in LAVA job 207670 (SoC: purwa-evk).
Job 207671 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207671 Failed test cases in LAVA job 207671 (SoC: lemans-evk).
Job 207672 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207672 Failed test cases in LAVA job 207672 (SoC: qcs615-ride).
Job 207673 | SoC shikra-iqs-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207673 Failed test cases in LAVA job 207673 (SoC: shikra-iqs-evk).
Job 207674 | SoC hamoa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207674 Failed test cases in LAVA job 207674 (SoC: hamoa-evk).
Job 207675 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207675 Failed test cases in LAVA job 207675 (SoC: monaco-evk).
Job 207676 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/207676 Failed test cases in LAVA job 207676 (SoC: qcs6490-rb3gen2).
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According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2),
two link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a
hardware-only mechanism and is invisible to software (PCIe r7.0,
Section 4.2.7.8.1). This change adds support for the WAKE# mechanism
in the PCI core.
According to the PCIe specification, multiple WAKE# signals can exist in
a system or each component in the hierarchy could share a single WAKE#
signal. In configurations involving a PCIe switch, each downstream port
(DSP) of the switch may be connected to a separate WAKE# line, allowing
each endpoint to signal WAKE# independently. From figure 5.4 in sec
5.3.3.2, WAKE# can also be terminated at the switch itself. Such topologies
are typically not described in Device Tree, therefore it is out of scope
for this series.
To support this, the WAKE# should be described in the device tree node of
the endpoint/bridge. If all endpoints share a single WAKE# line, then each
endpoint node shall describe the same WAKE# signal or a single WAKE# in
the Root Port node.
In pci_device_add(), PCI framework will search for the WAKE# in device
node. Once found, register for the wake IRQ through
dev_pm_set_dedicated_wake_irq() associates a wakeup IRQ with a device
and requests it, but the PM core keeps the IRQ disabled by default. The
IRQ is enabled by the PM core, only when the device is permitted to wake
the system, i.e. during system suspend and after runtime suspend, and
only when device wakeup is enabled.
If the same WAKE# GPIO is described in multiple device tree nodes, only the
first device that successfully registers the wake IRQ will succeed, while
subsequent registrations may fail. This limitation does not affect
functional correctness, since WAKE# is only used to bring the link to D0,
and endpoint-specific wakeup handling is resolved later through
PME detection (PME_EN is set in suspend path by PCI core by default).
When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() to
bring the device back to an active power state, such as transitioning from
D3cold to D0. Once the device is active and the link is usable, the
endpoint may generate a PME, which is then handled by the PCI core through
PME polling or the PCIe PME service driver to complete the wakeup of the
endpoint.
WAKE# is added in dts schema and merged based on below links.
Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/
Link: devicetree-org/dt-schema#170
Reviewed-by: Linus Walleij linus.walleij@linaro.org
Acked-by: Manivannan Sadhasivam mani@kernel.org
Signed-off-by: Krishna Chaitanya Chundru krishna.chundru@oss.qualcomm.com
Signed-off-by: Ziyue Zhang ziyue.zhang@oss.qualcomm.com
Link: https://lore.kernel.org/all/20260624-wakeirq_support-v11-1-120fbfaebe59@oss.qualcomm.com/
CRs-Fixed: 4542930