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Prepare qcom-next based on tag 'Linux 7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #978
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Qualcomm Glymur SoC has two Camera Control Interface (CCI) controllers. Each controller contains two I2C hosts. Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Define pinctrl definitions to enable camera master clocks on glymur. Signed-off-by: Nihal Kumar Gupta <nihalkum@qti.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Define ov08x40 on cci1_i2c1. The RGB sensor is connected to CSIPHY4 in four lane mode. Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…glymur Add an IMEM on glymur which falls back to mmio-sram and define the PIL relocation info region as its child, for post mortem tools to locate the loaded remoteprocs. Link: https://lore.kernel.org/lkml/20260424-glymur-imem-v5-2-18ede63cf063@oss.qualcomm.com/#r Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Without this property the scheduler treats all cores as equal. Values derived from performance measurements at 825.6 MHz: - M-class cores (cpu0-cpu5, oryon-2-2): capacity-dmips-mhz = 1024 - L-class cores (cpu6-cpu17, oryon-2-1): capacity-dmips-mhz = 1372 Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
… devices Add label properties to TPDM and CTI nodes in the glymur device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Link: https://lore.kernel.org/all/20260624-add-label-node-for-glymur-v2-1-e8420fd7025f@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add a compatible for this board. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add initial device tree support for it. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The Mahua QCB (Qualcomm Compute Board) is a board built on the Qualcomm Mahua SoC, a 12-core variant of the Glymur QCB in an open form factor. Unlike the CRD, the QCB is suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add a compatible for this board. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add initial device tree support for the Mahua QCB. The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Mahua SoC, a 12-core variant of the Glymur QCB in an open form factor. Unlike the CRD, the QCB is suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Link: https://lore.kernel.org/all/20260701-glymur-audio-v1-1-2c3862d95a09@oss.qualcomm.com/ Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Vinayak Katoch <vinayak.katoch@oss.qualcomm.com>
…PHY on Glymur The PCIe PHYs on Glymur require a reference voltage provided by REFGEN, which in turn is powered by two LDOs. Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and vdda-refgen1p2 supplies for each PCIe PHY node. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Mahua has a different QREF topology from Glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for glymur-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for mahua-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
… voltage for SD-card SD cards may need 1.8v VDDIO also to be supported, to accommodate this requirement reduce the min voltage to 1.8v for `vreg_l2b_e0` which supplies to VDDIO pin of SD card. NOTE - Since this SD card is the only client on this regulator, this change should not have any side effect on any other clients. moreover, SD card driver takes care to explicitly vote for the regulator voltage based on the SD card detection sequence. Also for stable operation of the SD card increase VDD voltage supplied by `vreg_l9b_e0` to 2.96v. Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-2-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Document the Glymur-specific SDHCI compatible in the sdhci-msm binding. Use "qcom,sdhci-msm-v5" as the fallback compatible for the MSM SDHCI v5 controller used on Glymur. Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260703-loutish-stimulating-hummingbird-aada5e@quoll/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Add support for SD card on Glymur SoC and enable the required pinctrl configurations. Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-4-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Enable SD card for Glymur CRD platform. Configure the vmmc/vqmmc regulators and gpio-based card detection for the platform. Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-5-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
The traceNoC node is the system-level Aggregator TNOC, so it must own a valid ATID that tags the whole aggregation path. It was marked compatible with "qcom,coresight-itnoc", an Interconnect TNOC, which is never assigned an ATID. As a result the aggregator had no trace ID and could not tag the merged trace. An Interconnect TNOC is a subsystem-level aggregator: it merges trace from the ATB sources within its subsystem (TPDMs and other ATB masters) and forwards the combined stream to the system-level Aggregator TNOC. It carries no ATID of its own, because the Aggregator TNOC downstream in the path already owns the ATID. Switch the node to "qcom,coresight-tnoc" so it is described as the Aggregator TNOC it is and is assigned a system trace ID. Rename the node to "tn" and use the "apb_pclk" clock name as required by the Aggregator TNOC binding. Link: https://lore.kernel.org/all/20260710-fix-tracenoc-probe-issue-v6-5-41eb36fef8d9@oss.qualcomm.com/ Fixes: 1f7d0c4 ("arm64: dts: qcom: glymur: add coresight nodes") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Link: https://lore.kernel.org/all/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
According to user manual / programming guide there is no separate PCIe phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two 4-lane blocks. This is also visible in memory map, where the 0xf00000 is marked as the main block with additional sub blocks for each 4-lane phys. Describing the sub phys without the rest is not correct from hardware description, even if it works. Link: https://lore.kernel.org/all/20260609141608.354186-2-krzysztof.kozlowski@oss.qualcomm.com/ Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Glymur's PCIe3a and PCIe3b controllers share a single Gen5x8 QMP PHY block that can be bifurcated into two independent x4 links, rather than each controller owning its own dedicated PHY. Add a pcie3_phy node describing the shared PHY block, add the missing PCIe3a controller node, and point both PCIe3a's and PCIe3b's port phys at &pcie3_phy (index 0 and 1 respectively) so each controller picks up its half of the bifurcated PHY. Update the GCC pipe clock parent array to reference the new PHY's clock outputs instead of the placeholders. Link: https://lore.kernel.org/all/20260717-glymur_linkmode_0717-v5-0-4f9e87a61463@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
CRD wires the shared Gen5x8 PCIe PHY's regulator supplies through board-specific PMIC rails. Add the vdda-phy, vdda-pll, and vdda-refgen0p9/1p2 supplies for &pcie3_phy. Link: https://lore.kernel.org/all/20260717-glymur_linkmode_0717-v5-0-4f9e87a61463@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add PCIe3a required resources eg. power supplies, GPIOs. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Enable PCIe3b controller and PCIe3b PHY. Add required LDOs and GPIOs. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The currently listed SoCCP and SoCCP DTB reserved memory regions don't align with the memory requested by the SoCCP Firmware. Fix this by updating the SoCCP/SoCCP DTB memory regions to reflect the memory region requirements of the SoCCP firmware, as described in the Glymur v21 memory map release. Link: https://lore.kernel.org/lkml/20260709-glymur-soccp-v6-3-16f70227547d@oss.qualcomm.com/ Fixes: 41b6e8d ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
…ng system resume On Glymur, display NoC errors are observed during system resume when MDSS register accesses occur before the MMCX/Display NoC path has scaled back to a voltage level sufficient for the required bandwidth. Keep the display clock controller's power-domain requirement at the turbo operating point as a temporary workaround to ensure the interconnect remains at a stable performance level during the resume sequence and avoid NoC errors triggered by early MDSS register access. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add Battery Current Limiting (BCL) hardware monitor node for pmh0101 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-6-febe2805e17b@oss.qualcomm.com
qlijarvis
commented
Aug 21, 2026
🔨 Build Failure Analysis — PR #978PR:#978
Verdict1 error is introduced by this PR. The error occurs in both standard and RT kernel builds. 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 21, 2026
🔨 Build Failure Analysis — PR #978PR:#978
VerdictThis build failure is NOT introduced by this PR. The error is caused by a pre-existing issue in the base tree where a Makefile rule references 📎 Detailed analysis:Full report |
qlijarvis
commented
Aug 22, 2026
LAVA Failed Case Triage SummaryPR: #978 Job 207833 | SoC kaanapali-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207833 Failed test cases in LAVA job 207833 (SoC: kaanapali-mtp).
Job 207834 | SoC glymur-crdLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207834 Failed test cases in LAVA job 207834 (SoC: glymur-crd).
Job 207835 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/207835 Failed test cases in LAVA job 207835 (SoC: qcs6490-rb3gen2).
Job 207836 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207836 Failed test cases in LAVA job 207836 (SoC: qcs615-ride).
Job 207837 | SoC hamoa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207837 Failed test cases in LAVA job 207837 (SoC: hamoa-evk).
Job 207838 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207838 Failed test cases in LAVA job 207838 (SoC: qcs9100-ride).
Job 207839 | SoC sm8750-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207839 Failed test cases in LAVA job 207839 (SoC: sm8750-mtp).
Job 207840 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207840 Failed test cases in LAVA job 207840 (SoC: monaco-evk).
Job 207841 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207841 Failed test cases in LAVA job 207841 (SoC: lemans-evk).
Job 207842 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207842 Failed test cases in LAVA job 207842 (SoC: qcs8300-ride).
Job 207843 | SoC shikra-iqs-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207843 Failed test cases in LAVA job 207843 (SoC: shikra-iqs-evk).
Job 207844 | SoC purwa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/207844 Failed test cases in LAVA job 207844 (SoC: purwa-evk).
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Aug 22, 2026
qcomlnxci
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Aug 22, 2026
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qcomlnxci
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Aug 24, 2026
qcomlnxci
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…gulator" This reverts commit 32998bb in favour of the upstream fix, which is applied in the following patch. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…CIe PHYs The QMP PCIe PHYs on QCS8300 require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (QCS8300-RIDE, Monaco-EVK and Monaco-Monza-SoM), and add refgen-supply in the SoC DTSI (monaco.dtsi) since refgen is an on-chip regulator shared across boards. The PHY driver votes for refgen3 directly as a workaround for a hardware issue where QREF actually depends on refgen3 rather than refgen2 as documented. Link: https://lore.kernel.org/all/20260810112735.1326807-4-ziyue.zhang@oss.qualcomm.com/ Fixes: 33967ea ("arm64: dts: qcom: qcs8300-ride: enable pcie0 interface") Fixes: cdb613a ("arm64: dts: qcom: qcs8300-ride: enable pcie1 interface") Fixes: 41e2424 ("arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.") Fixes: 5238f4e ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
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e812d7fCompareqlijarvis
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Aug 25, 2026
LAVA Failed Case Triage SummaryPR: #978 Job 208048 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208048 Failed test cases in LAVA job 208048 (SoC: qcs615-ride).
Job 208049 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208049 Failed test cases in LAVA job 208049 (SoC: lemans-evk).
Job 208050 | SoC purwa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208050 Failed test cases in LAVA job 208050 (SoC: purwa-evk).
Job 208051 | SoC shikra-iqs-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208051 Failed test cases in LAVA job 208051 (SoC: shikra-iqs-evk).
Job 208052 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/208052 Failed test cases in LAVA job 208052 (SoC: qcs6490-rb3gen2).
Job 208053 | SoC glymur-crdLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208053 Failed test cases in LAVA job 208053 (SoC: glymur-crd).
Job 208054 | SoC kaanapali-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208054 Failed test cases in LAVA job 208054 (SoC: kaanapali-mtp).
Job 208055 | SoC hamoa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208055 Failed test cases in LAVA job 208055 (SoC: hamoa-evk).
Job 208056 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208056 Failed test cases in LAVA job 208056 (SoC: monaco-evk).
Job 208057 | SoC sm8750-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208057 Failed test cases in LAVA job 208057 (SoC: sm8750-mtp).
Job 208058 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208058 Failed test cases in LAVA job 208058 (SoC: qcs8300-ride).
Job 208059 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208059 Failed test cases in LAVA job 208059 (SoC: qcs9100-ride).
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qlijarvis
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Aug 25, 2026
LAVA Failed Case Triage SummaryPR: #978 Job 208280 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208280 Failed test cases in LAVA job 208280 (SoC: qcs8300-ride).
Job 208281 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208281 Failed test cases in LAVA job 208281 (SoC: qcs9100-ride).
Job 208282 | SoC sm8750-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208282 Failed test cases in LAVA job 208282 (SoC: sm8750-mtp).
Job 208283 | SoC shikra-iqs-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208283 Failed test cases in LAVA job 208283 (SoC: shikra-iqs-evk).
Job 208284 | SoC purwa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208284 Failed test cases in LAVA job 208284 (SoC: purwa-evk).
Job 208285 | SoC glymur-crdLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208285 Failed test cases in LAVA job 208285 (SoC: glymur-crd).
Job 208286 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/208286 Failed test cases in LAVA job 208286 (SoC: qcs6490-rb3gen2).
Job 208287 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208287 Failed test cases in LAVA job 208287 (SoC: monaco-evk).
Job 208288 | SoC kaanapali-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208288 Failed test cases in LAVA job 208288 (SoC: kaanapali-mtp).
Job 208289 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208289 Failed test cases in LAVA job 208289 (SoC: lemans-evk).
Job 208290 | SoC hamoa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208290 Failed test cases in LAVA job 208290 (SoC: hamoa-evk).
Job 208291 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/208291 Failed test cases in LAVA job 208291 (SoC: qcs615-ride).
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qcomlnxci
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Aug 25, 2026
qcomlnxci
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Aug 25, 2026
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qcomlnxci
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qcomlnxci
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qcomlnxci
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qcomlnxci
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qcomlnxci
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Aug 26, 2026
qcomlnxci
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Aug 26, 2026
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…ault"" The kaanapali-MTP crash that prompted the workaround was due to frame done timeouts on DSI. That issue is now fixed and frame done timeouts are no longer seen on kaanapali DSI with virtual planes enabled. Virtual planes are also required for 4K display support on Kodiak (SC7280). Re-enable virtual planes by default. This reverts commit 7a17c61. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Aug 26, 2026
qcomlnxci
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Aug 26, 2026
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Name SHA Commits
tech/bsp/clk 24b9b5e 32
tech/bsp/devfreq 4809534 7
tech/security/firmware-smc de7413c 6
tech/bsp/soc-infra ff6ff7b 22
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 39a86aa 13
tech/bus/peripherals e6f6741 8
tech/bus/pci/all 99d5cf2 45
tech/bus/pci/phy 66e44c2 14
tech/bus/usb/dwc d90fb64 4
tech/bus/usb/phy c3aa7d5 35
tech/debug/hwtracing a3f730f 24
tech/pmic/misc 8d60b51 22
tech/mem/iommu cdc9e80 9
tech/mm/audio/all 88b8f29 8
tech/mm/camss dffc6e9 49
tech/mm/drm 83f65e1 76
tech/mm/fastrpc bff2f47 12
tech/mm/video bdcc5c4 127
tech/mm/gpu b9f2291 12
tech/mproc/rpmsg 55dc464 1
tech/net/ath 2ac1acc 21
tech/net/bluetooth 450dc5e 7
tech/pm/power f712532 16
tech/pm/thermal d525ff9 8
tech/security/crypto 1f60c0a 23
tech/security/ice beabac0 9
tech/storage/all cef1b3c 5
tech/all/dt/qcs6490 2e92fd1 28
tech/all/dt/qcs9100 754b808 24
tech/all/dt/qcs8300 a02cf61 31
tech/all/dt/qcs615 66b7e2f 11
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza 5338032 25
tech/all/dt/hamoa 106f486 49
tech/all/dt/glymur c5bf216 60
tech/all/dt/kaanapali d21ef73 26
tech/all/dt/pakala 450d786 9
tech/all/config 7b48e6e 78
tech/overlay/dt b895d0e 78
tech/all/workaround 219d869 12
tech/mproc/all 104969c 2
tech/noup/debug/all e473076 29
tech/hwe/unoq a2d85fe 4
early/hwe/shikra/drivers b19d2ec 184
early/hwe/shikra/dt dd90d88 130
early/hwe/lyra 8c9d598 6