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1. fpga-cnn-acceleratorfpga-cnn-acceleratorPublic

   FPGA-based Convolutional Neural Network accelerator using a resource-efficient Serial MAC architecture. Optimized for edge inference with 100% PyTorch golden model verification.

   Verilog 3

2. pipelined-RISCV-corepipelined-RISCV-corePublic

   A 32-bit pipelined RISC-V CPU (RV32I subset) with forwarding and load-use hazard handling, implemented and verified in Verilog.

   Verilog

3. 32-bit-RISCV-Single-Cycle-Core32-bit-RISCV-Single-Cycle-CorePublic

   A Verilog implementation of a 32-bit Single-Cycle RISC-V Processor.

   Verilog

4. Booth-WallaceBooth-WallacePublic

   ASIC Design Flow of Signed 8x8 Booth-Wallace Multiplier (Radix-4)

   Verilog 2

5. ASYNC-FIFOASYNC-FIFOPublic

   A Verilog implementation of Asynchronous FIFO in Xilinx Vivado

   Verilog

6. Signed-Booth-MultiplierSigned-Booth-MultiplierPublic

   Hardware implementation of a Signed 8x8-bit Multiplier using Radix-4 Booth Encoding in Verilog

   Verilog