This repo contains a ARM based CPU written in VHDL.
It is divided into 2 modules: datapath and controller, with each having their own submodules/entities.
- Is a integrated design consisting of functional units:
- ALU
- Multipliers
- Shifter
- Register File, registers
- Muxes and extenders.
Controller determines the operation of the datapath, by passing control signals to various multiplexers. It controls the data flow through the datapath.
It consists of the following sub-modules:
- Instruction Decode
- Main Controller
- ALU Controller
- Branch Controller
- Controller FSM:
- Schematic:
