retroSoC is a fully open-source and customizable ASIC framework for “retro-style” applications. it is both straightforward to use and highly compatible with EDA toolchains — specifically targeting open-source EDA (iEDA, OpenROAD, etc).
Additionally, retroSoC can also serve as a flexible, reconfigurable SoC template for end customers or students who want to integrate their own design into a shared fabrication wafer (shuttle).
| retroSoC | information |
|---|---|
| TINY | A Minimum RV32E Educational MCU(<10K instances) |
| CORE(ongoing): SCP, Single Cylcle Processor | |
| BUS: NATIVE bridge(NATIVE mux, AXI4L2NATIVE, NATIVE2APB), single power/clock domain, 16-64MHz(IC55, IHP/SKY130, SMIC110) | |
| SYSTEM IP: 1xARCHINFO | |
| MEMORY IP: 16MB SPI NOR FLASH, 512KB/1MB QPI FRAM, 8/16MB QPI PSRAM | |
| INTERFACE IP: 2xUART, 4xGPIO, 2xTIMER, 1xI2C, 1xQSPI | |
| PACKAGE: QFN48 | |
| DEMO: smart band | |
| MINI | A Lightweight RV32I/EMC MCU(10K~50K instances) |
| CORE: PicoRV32, KianV(RV32I, tt07, RVIMA, tt06), SERV, ongoing: DarkRISCV, tinyQV, FemtoRV32, TinySys, VexiiRiscv | |
| BUS: NMI bridge(NMI2AXI, NMI2APB), single power/clock domain, 24-192MHz(ICS55, IHP/SKY130, SMIC110) | |
| SYSTEM IP: 1xARCHINFO, 1xRCU, 1xSYSCTRL, 1xCLINT, 1xDMA | |
| MEMORY IP: 0-128KB OCM, 16MB SPI NOR FLASH, 512KB/1MB QPI FRAM, 8-32MB(8MBx4) QPI PSRAM | |
| INTERFACE IP: 2xUART, 30xGPIO, 3xTIMER, 1xRNG, 4xPWM, 1xWDG, 1xPS2, 2xI2C, 2xQSPI, 1xSPISD, 1XONE-WIRE | |
| MULTIMEDIA IP: 1xI2S | |
| PACKAGE: QFN88/128 | |
| DEMO: smart band, micro quadcopter | |
| STD | A Complete RV32IMAC MCU(20K~80K instances) |
| CORE(ongoing): Hummingbirdv2 E203, CV32E40P, ibex, Harzard3, SCR1, RV12(RVLogic), Glacial, VeeR EH1, VexRiscv | |
| BUS: AHB/AXI matrix(AHB/AXI splitter, AHB/AXI2APB), single power, multi clock domain, 72-600MHz(ICS55, IHP/SKY130, SMIC110) | |
| SYSTEM IP: 1xARCHINFO, 1xRCU, 1XPLIC, 1xSYSCTRL, 1xDMA | |
| MEMORY IP: 0-512KB OCM, 16MB QSPI NOR FLASH, 512KB/1MB QPI FRAM, 8-32MB(8MBx4) QPI PSRAM, 32MB DDR OPI PSRAM, 32MB SDRAM | |
| INTERFACE IP: 3xUART, 30xGPIO, 6xTIMER, 1xRNG, 8xPWM, 2xWDG, 1xRTC, 1xPS2, 2xI2C, 1xI3C, 2xQSPI, 1xSDIO, 1xONE-WIRE, 1xCRC, 1xUSB1.1 | |
| MULTIMEDIA IP: 1xI2S, 1xVGALCD, 1xDVP, 1x2D GRAPHIC ACCEL, 1xAUDIO DECODER | |
| PACKAGE: QFN128 | |
| DEMO: game console | |
| PRO | A High-performance RV32/64GC SoC(60K~200K instances) |
| CORE(ongoing): Nanhu-G(XiangShan), biriscv, CVA6, VexRiscv, Rocket Chip, BOOM, RRV64, GreenRio | |
| BUS: AXI bridge(AXI splitter, AXI2APB), single power, multi clock domain, 100-800MHz(IC55, IHP/SKY130, SMIC110) | |
| SYSTEM IP: 1xARCHINFO, 1xRCU, 1XPLIC, 1xSYSCTRL, 1xDMA | |
| MEMORY IP: 0-1024KB OCM, 16MB SPI NOR FLASH, 8-32MB(8MBx4) QPI PSRAM, 32MB DDR OPI PSRAM, 32MB SDRAM | |
| INTERFACE IP: 3xUART, 32xGPIO, 8xTIMER, 1xRNG, 10xPWM, 2xWDG, 1xRTC, 1xPS2, 2xI2C, 1xI3C, 2xQSPI, 1xSDIO, 1xCRC, 1xUSB1.1 | |
| MULTIMEDIA IP: 1xI2S, 1xVGALCD, 1xDVP, 1x2D GRAPHIC ACCEL，1xAUDIO DECODER, 1xGPU(support OpenGL1.x) | |
| PACKAGE: QFP144 | |
| DEMO: Game Console, single board computer |
IPs list and development state:
| clusterIP | MILESTONE |
|---|---|
| system | Common Component, Interrupt Controller, Reset&Clock Unit |
| common |          |
| archinfo | |
| clint | |
| plic |   |
| rcu | |
| interface | Low-speed Peripherals |
| gpio | |
| uart | |
| ps2 | |
| timer | |
| pwm | |
| wdg | |
| rtc | |
| i2c | |
| application | Specific Field IPs |
| rng | |
| crc | |
| multimedia | SPI/QSPI TFT-LCD, VGA/LCD, SDIO TF/WiFi, CMOS Camera, DMA, 2D Graphic Accel. |
| spi | |
| i2s | |
| vga | |
| dma |    |
| dvp | |
| sdio | |
| memory | on-chip SRAM, QPI SDR FRAM/PSRAM, OPI DDR PSRAM, 16-bit SDR SDRAM |
| sram | |
| fram | |
| psram | |
| sdram | |
| other | |
| tapeout1 | |
- this archive repo contains some old tapeout-verified IPs:
| state badge statement | ||||
|---|---|---|---|---|
| SPC: SPEC complete | RTF: RTL frozen | SMT: SMOKE test | UVV: UVM verif | FUC: FUNCTION coverage |
| COC: CODE coverage | SOI: SoC integ | FPE: FPGA emu | TPT: TAPEOUT test |
More Info
Refer to the template repo. If you want to create a new ip repo, You need to:
- Use this repository template to create a new repo
- Update the content
[IP NAME]inheaderfile and remove theheaderfile.
refer to the style.md.
If you want to contribute to this project, be sure to review the guidelines. This is an open project and contributions and collaborations are always welcome!! This project adheres to retroSoC's code_of_conduct. By participating, you are expected to uphold this code.
we use GitHub issues for tracking requests and bugs, so please direct specific questions to issues panel.
The retroSoC project strives to abide by generally accepted best practices in open-source software development, you can issue bugs, pull requests, new features and modification suggestions freely. Your feedbacks could help us ensure a bright future for this project. We value and treasure every issue or contribution, big or small. 😄
All of the IPs codes are redistributed or released under the OSI Approved LICENSE MulanPSL2.