VLSI Engineer | RTL Design, Verification & Digital Synthesis | FPGA • ASIC | Turning logic into silicon.
- India
Popular repositories Loading
- Attendance-Using-Face-Recognition
Attendance-Using-Face-Recognition PublicI have made an attendance system which marks attendance of employees/students using their facial embeddings. We are using open cv libraries of python for face recognition. This project also include…
Python
- open-source-tool-installation-guide
open-source-tool-installation-guide Publica complete guide for users to create a complete open-source ASIC-learning-environment.
Shell
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.
Uh oh!
There was an error while loading. Please reload this page.