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shausindustries/README.md

Hi, I'm Shau 👋

Digital IC & Microarchitecture Engineer | Aspiring Master's in Microelectronics & CompArch (Germany)
Focused on Processor Microarchitecture, RTL Design, Cache/Memory Subsystems, and Open-Source ASIC Implementation (SkyWater 130nm).

🔬 Core Technical Focus

  • Processor Microarchitecture: 5-Stage In-Order Pipelines, Dynamic Branch Prediction (BHT/BTB), Hazard Resolution, Out-of-Order Execution concepts (ROB, Reservation Stations, CDB).
  • RTL & Hardware Design: SystemVerilog (IEEE 1800), Verilog-2001, Structural & Behavioural Modeling.
  • Memory & Interconnect: L1 Cache Controllers (Direct-Mapped / Write-Back), SRAM Bitcell Layout, Memory-Mapped Peripherals (GPIO, UART, I2C, Timers).
  • EDA & Physical Implementation: Yosys Open Synthesis, SkyWater 130nm PDK (sky130A), Magic VLSI Layout, Ngspice, Xilinx Vivado.
  • Architectural Exploration: C-based Instruction-Level Simulators, Microarchitectural Tradeoff Analysis (Hennessy & Patterson Quantitative Approach).

🛠️ Toolchain & Technical Stack

CategoryTechnologies & Tools
HDL & LanguagesSystemVerilog, Verilog, C/C++, Python
Simulation & VerificationIcarus Verilog (iverilog), GTKWave, ModelSim, Vivado XSIM, Verilator
Synthesis & ASIC FlowYosys, OpenLane / OpenROAD, Sky130 PDK, Xilinx Vivado
Custom IC & TransistorMagic VLSI, Ngspice
Architectures & ISAsRISC-V (RV32I), MIPS-32

🏛️ Featured Hardware Projects

  • 🚀 M32_MCU_V1: 32-bit SoC integrating a pipelined CPU core with an on-chip peripheral subsystem (UART, I2C, Timers, GPIO) synthesized to Sky130 standard cells.
  • ⚙️ Mips_32_processor: Evolutionary CPU architecture: Single-Cycle $\rightarrow$ 5-Stage Pipeline with Forwarding/Stalls $\rightarrow$ 2-Bit Dynamic Branch Prediction $\rightarrow$ Tomasulo Out-of-Order Engine.
  • ⚡ DirectCache: Synthesizable direct-mapped L1 cache controller with tag comparison, valid/dirty bit tracking, and write-back/write-allocate FSM.
  • 📐 6TSRAMBitcell: Custom IC layout of a 6T SRAM cell in Magic VLSI with transient stability analysis.
  • 💻 ToyProcessor: Cycle-accurate, C-based instruction-level processor simulator for architectural exploration and disassembling.

📬 Contact & Links

Pinned Loading

  1. Mips_32_processorMips_32_processorPublic

    Evolutionary 32-bit Processor Core: 5-Stage Pipeline, Hazard Forwarding, Dynamic Branch Prediction (BHT/BTB), & Out-of-Order Engine.

    Verilog 1

  2. M32_MCU_V1M32_MCU_V1Public

    32-bit Pipelined Microcontroller SoC with Memory-Mapped Peripherals (UART, I2C, Timer, GPIO) synthesized on SkyWater 130nm.

    Verilog

  3. DirectCacheDirectCachePublic

    Direct-Mapped L1 Cache Controller with Tag Matching, Hit/Miss FSM, and Write-Back / Write-Allocate Policy.

    Verilog 1

  4. 6TSRAMBitcell6TSRAMBitcellPublic

    Transistor-level 6T Static RAM Bitcell Full Custom Layout in Magic VLSI with Transient Read/Write Stability Analysis.

    1

  5. cmos_invertercmos_inverterPublic

  6. ToyProcessorToyProcessorPublic

    Instruction-Level Architectural Simulator & Disassembler in C for RISC Instruction Set Exploration.

    C