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lemp12: Enable TCSS Type-C port, PMC mux and retimer - #281
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August 12, 2026 17:38
The adl baseboard selects both of these; rpl selects neither. They gate the build of the devicetree chip drivers used to describe a TCSS Type-C port: - drivers/intel/pmc_mux/Makefile.mk builds mux.c and conn/conn.c only when CONFIG_DRIVERS_INTEL_PMC is set - drivers/intel/usb4/retimer is gated on CONFIG_DRIVERS_INTEL_USB4_RETIMER Without them, a variant that adds "chip drivers/intel/pmc_mux" or "chip drivers/intel/usb4/retimer" to its overridetree fails to link. This commit has no functional effect on its own, and none on any variant that does not use those drivers. It is a prerequisite for the lemp12 change that follows. TEST=Builds for lemp12. No change to the built image: with no variant using these drivers yet, the .config gains the two symbols but no additional objects are linked. Change-Id: Iada38a12a1157c5190084aa7c893c13c2f29d236 Signed-off-by: mw <mw@mattsp.dev>
lemp12's sole USB-C connector (J_TYPEC1) never operates above USB 2.0 and DisplayPort alt-mode never engages. Reported in firmware-open#675. soc/intel/alderlake fill_fsps_tcss_params() derives UsbTcPortEn from whether the devicetree device tcss_usb3_port1 is enabled: s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) if (is_dev_enabled(tcss_port_arr[i])) s_cfg->UsbTcPortEn |= BIT(i); chipset.cb defaults tcss_root_hub and tcss_usb3_port1 to off, the rpl baseboard declares no TCSS section, and no rpl variant enables them, so the bit stays clear and FSP-S never enables the Type-C port. The connector's USB2 pair routes to the PCH and keeps working, which is why the port enumerates devices at 480 Mbps while its SuperSpeed lanes stay dark. Enable the port and describe it the way the adl variants do. The per-port drivers/usb/acpi descriptors under xhci are added at the same time, since the pmc_mux conn node references usb2_port3 and the board has no per-port descriptors at all today. Upstream CB:94134 adds those descriptors to all twelve rpl variants; if that lands here first, that hunk can be dropped. GPP_E4 is this board's retimer force-power pad, declared in its own gpio.c as TBT_FORCE_PWR and confirmed against the Clevo L140AU schematic (board 6-71-L14A0-D02A): PCH ball FC22 -> GPPE4_TBT_FORCE_PWR -> R411 (0R, populated) -> TC_RETIMER_FORCE_PWR -> JHL8040R FORCE_PWR ball A9. All adl variants (7/7) enable tcss_usb3_port1; no rpl variant (0/12) does. The same split holds for tgl-u and mtl, which suggests the rpl directory was created without carrying the Type-C stack over. Reading their overridetrees, darp9, galp7 and oryp11 look affected the same way -- in each case the Type-C connector with no PCH usb3_ports[] entry is the one users report as broken (firmware-open#472 for oryp11, #497 for darp9). I have deliberately left those boards alone: I do not own them and cannot test them, so this change is scoped to the one board I can verify on. The same blocks should apply, with the conn alias and the retimer pad adjusted per board. TEST=Builds for lemp12 on the current release (2025-07-24_c242738). Generated static.c has _dev_tcss_usb3_port1 .enabled = 0 before this change and 1 after, and gains drivers_intel_pmc_mux_ops, drivers_intel_pmc_mux_conn_ops and drivers_intel_usb4_retimer_ops. Comparing a stock and a patched ROM built from the same tree: identical CBFS file set, FSP, microcode, payload and bootblock bit-for-bit unchanged, fallback/ramstage +2189 B and romstage +768 B. The string INTC105C appears only in the patched ramstage, and decoding the device array out of the extracted ramstage shows tcss_usb3_port1 .enabled going 0 -> 1, so the bit reaches the image that would be flashed. NOT tested on hardware. This machine's SPI flash is a leadless WSON-8 part with no external programmer attached and the flash map has a single COREBOOT region, so I have not flashed it. The runtime behaviour is unverified; I will follow up once I have flashed it, and would welcome anyone with a bench unit testing it first. Change-Id: I69f5f7ceef1f39a2be4a28a24270e9650589f915 Signed-off-by: mw <mw@mattsp.dev>
jackpot51
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Aug 12, 2026
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Please disclose any LLM usage in the creation of this PR including all associated code changes and PR descriptions. |
mattwollf
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Aug 12, 2026
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pretty much everything is LLM generated and edited by me |
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lemp12's USB-C connector (
J_TYPEC1) never operates above USB 2.0 and DisplayPortalt-mode never engages. Reported in firmware-open#675, which has the measurements.
fill_fsps_tcss_params()derivesUsbTcPortEnfrom whether the devicetree devicetcss_usb3_port1is enabled.soc/intel/alderlake/chipset.cbdefaults itoff, therplbaseboard declares no TCSS section, and norplvariant enables it, so the bitstays clear and FSP-S never brings the port up. The connector's USB2 pair routes to the
PCH (
usb2_ports[2] = USB2_PORT_TYPE_C) and keeps working, so devices enumerate at480 Mbps with the SuperSpeed lanes dark.
7/7
adlvariants enabletcss_usb3_port1; 0/12rplvariants do.tgl-uandmtlenable it as well.
Commits:
mb/system76/rpl: selectDRIVERS_INTEL_PMCandDRIVERS_INTEL_USB4_RETIMER.adlselects both,
rplneither; the chip entries below do not link without them.mb/system76/lemp12: enabletcss_root_hub/tcss_usb3_port1undertcss_xhci, adddrivers/intel/usb4/retimerundertcss_dma0, adddrivers/intel/pmc_mux+connunder
pmc, add the per-portdrivers/usb/acpidescriptors underxhci. Mirrorslemp11.
GPP_E4is this board's retimer force-power pad, per its own gpio.c (TBT_FORCE_PWR)and the Clevo L140AU schematic (
6-71-L14A0-D02A): PCH ball FC22 →GPPE4_TBT_FORCE_PWR→ R411 (0 Ω, populated) →TC_RETIMER_FORCE_PWR→ JHL8040RFORCE_PWRball A9.CB:94134 adds the per-port
drivers/usb/acpidescriptors to all twelverplvariants;that hunk can be dropped if it lands here first. It is included because
pmc_mux/connreferences
usb2_port3and lemp12 has no per-port descriptors on this branch.Verified:
28fb5085(release2025-07-24_c242738).static.c:_dev_tcss_usb3_port1.enabled0 → 1; gainsdrivers_intel_pmc_mux_ops,drivers_intel_pmc_mux_conn_opsanddrivers_intel_usb4_retimer_ops;conn.usb2_port=&_dev_usb2_port3,conn.usb3_portandretimer.dfp[0].typec_port=&_dev_tcss_usb3_port1.payload and bootblock unchanged,
fallback/ramstage+2189 B,romstage+768 B.INTC105Cpresent only in the patched ramstage. Decoding the device array out of theextracted ramstage shows
tcss_usb3_port1.enabled0 → 1.Not tested on hardware. This board's SPI part is a leadless WSON-8
MX25L25673G(U41),I have no external programmer, and the flash map has a single
COREBOOTregion, so Ihave not flashed a patched ROM. The runtime behaviour is unverified.
darp9, galp7 and oryp11 show the same pattern — a Type-C connector with no PCH
usb3_ports[]entry (firmware-open#472, #497). Not touched here; I cannot test them.