edf_schedule: reimplement the whole EDF scheduler

Kconfig

@@ -38,14 +38,6 @@ config HOST_PTABLE
 	bool
 	default n
 
-config TASK_HAVE_PRIORITY_MEDIUM
-	bool
-	default n
-
-config TASK_HAVE_PRIORITY_LOW
-	bool
-	default n
-
 config BOOT_LOADER
 	bool
 	default n

scripts/qemu-check.sh

@@ -57,23 +57,23 @@ do
 	then
  READY_IPC="00 00 00 f0"
  SHM_IPC_REG=qemu-bridge-ipc-io
- OUTBOX_OFFSET="f000"
+ OUTBOX_OFFSET="11000"
  SHM_MBOX=qemu-bridge-hp-sram-mem
  ROM="-r ../sof.git/build_${j}_gcc/src/arch/xtensa/rom-$j.bin"
 	fi
 	if [ $j == "skl" ]
 	then
  READY_IPC="00 00 00 f0"
  SHM_IPC_REG=qemu-bridge-ipc-io
- OUTBOX_OFFSET="f000"
+ OUTBOX_OFFSET="11000"
  SHM_MBOX=qemu-bridge-hp-sram-mem
  ROM="-r ../sof.git/build_${j}_gcc/src/arch/xtensa/rom-$j.bin"
 	fi
 	if [ $j == "kbl" ]
 	then
  READY_IPC="00 00 00 f0"
  SHM_IPC_REG=qemu-bridge-ipc-io
- OUTBOX_OFFSET="f000"
+ OUTBOX_OFFSET="11000"
  SHM_MBOX=qemu-bridge-hp-sram-mem
  ROM="-r ../sof.git/build_${j}_gcc/src/arch/xtensa/rom-$j.bin"
 	fi

src/arch/host/include/arch/schedule/task.h

@@ -16,25 +16,6 @@
 #ifndef __ARCH_SCHEDULE_TASK_H__
 #define __ARCH_SCHEDULE_TASK_H__
 
-struct task;
-
-/**
- * \brief Allocates IRQ tasks.
- */
-static inline int arch_allocate_tasks(void)
-{
-	return 0;
-}
-
-/**
- * \brief Runs task.
- * \param[in,out] task Task data.
- */
-static inline int arch_run_task(struct task *task)
-{
-	return 0;
-}
-
 #endif /* __ARCH_SCHEDULE_TASK_H__ */
 
 #else

src/arch/xtensa/drivers/idc.c

@@ -18,6 +18,7 @@
 #include <sof/lib/notifier.h>
 #include <sof/lib/shim.h>
 #include <sof/platform.h>
+#include <sof/schedule/edf_schedule.h>
 #include <sof/schedule/schedule.h>
 #include <sof/schedule/task.h>
 #include <ipc/control.h>
@@ -166,6 +167,8 @@ static int idc_pipeline_trigger(uint32_t cmd)
 	struct ipc *ipc = cache_to_uncache(_ipc);
 	struct sof_ipc_stream *data = ipc->comp_data;
 	struct ipc_comp_dev *pcm_dev;
+	struct edf_task_pdata *edf_pdata;
+	struct task *task;
 	int ret;
 
 	/* invalidate stream data */
@@ -183,6 +186,17 @@ static int idc_pipeline_trigger(uint32_t cmd)
 
  pipeline_cache(pcm_dev->cd->pipeline,
  pcm_dev->cd, CACHE_INVALIDATE);
+
+ /* TODO: Temporary W/A for task sharing between cores.
+ * Should be removed after changing memory management for
+ * slave cores.
+ */
+ if (pcm_dev->cd->pipeline->pipe_task.type == SOF_SCHEDULE_EDF) {
+ task = &pcm_dev->cd->pipeline->pipe_task;
+ edf_pdata = edf_sch_get_pdata(task);
+ dcache_invalidate_region(edf_pdata, sizeof(*edf_pdata));
+ task_context_cache(edf_pdata->ctx, CACHE_INVALIDATE);
+ }
 	}
 
 	/* check whether we are executing from the right core */
@@ -193,9 +207,22 @@ static int idc_pipeline_trigger(uint32_t cmd)
 	ret = pipeline_trigger(pcm_dev->cd->pipeline, pcm_dev->cd, cmd);
 
 	/* writeback pipeline on stop */
-	if (cmd == COMP_TRIGGER_STOP)
+	if (cmd == COMP_TRIGGER_STOP) {
+ /* TODO: Temporary W/A for task sharing between cores.
+ * Should be removed after changing memory management for
+ * slave cores.
+ */
+ if (pcm_dev->cd->pipeline->pipe_task.type == SOF_SCHEDULE_EDF) {
+ task = &pcm_dev->cd->pipeline->pipe_task;
+ edf_pdata = edf_sch_get_pdata(task);
+ task_context_cache(edf_pdata->ctx, CACHE_WRITEBACK_INV);
+ dcache_writeback_invalidate_region(edf_pdata,
+ sizeof(*edf_pdata));
+ }
+
  pipeline_cache(pcm_dev->cd->pipeline,
  pcm_dev->cd, CACHE_WRITEBACK_INV);
+	}
 
 	return ret;
 }

src/arch/xtensa/include/arch/schedule/task.h

@@ -3,75 +3,59 @@
  * Copyright(c) 2017 Intel Corporation. All rights reserved.
  *
  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Tomasz Lauda <tomasz.lauda@linux.intel.com>
  */
 
 /**
  * \file arch/xtensa/include/arch/schedule/task.h
  * \brief Arch task header file
  * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Tomasz Lauda <tomasz.lauda@linux.intel.com>
  */
 
 #ifdef __SOF_SCHEDULE_TASK_H__
 
 #ifndef __ARCH_SCHEDULE_TASK_H__
 #define __ARCH_SCHEDULE_TASK_H__
 
-#include <sof/list.h>
-#include <config.h>
-
-/** \brief IRQ task data. */
-struct irq_task {
-	struct list_item list;	/**< list of tasks */
-	int irq; /**< IRQ level */
-};
-
-struct sof;
 struct task;
 
-#if CONFIG_SMP
-
-/**
- * \brief Starts slave core main task.
- * \param[in,out] sof Main context.
- * \return Error code.
- */
-int do_task_slave_core(struct sof *sof);
-
-#endif
-
 /**
- * \brief Returns IRQ low task data.
- * \return Pointer to pointer of IRQ low task data.
+ * \brief Returns main task data.
+ * \return Pointer to pointer of main task data.
  */
-struct irq_task **task_irq_low_get(void);
+struct task **task_main_get(void);
 
 /**
- * \brief Returns IRQ medium task data.
- * \return Pointer to pointer of IRQ medium task data.
+ * \brief Returns current system context.
  */
-struct irq_task **task_irq_med_get(void);
+volatile void *task_context_get(void);
 
 /**
- * \brief Returns IRQ high task data.
- * \return Pointer to pointer of IRQ high task data.
+ * \brief Switches system context.
+ * \param[in,out] task Task context to be set.
  */
-struct irq_task **task_irq_high_get(void);
+void task_context_set(void *task_ctx);
 
 /**
- * \brief Runs task.
- * \param[in,out] task Task data.
+ * \brief Initializes task context.
+ * \param[in,out] task Task with context to be initialized.
+ * \param[in,out] entry Entry point for task execution.
  */
-int arch_run_task(struct task *task);
+int task_context_init(struct task *task, void *entry);
 
 /**
- * \brief Allocates IRQ tasks.
+ * \brief Frees task context.
+ * \param[in,out] task Task with context to be freed.
  */
-int arch_allocate_tasks(void);
+void task_context_free(struct task *task);
 
 /**
- * \brief Frees IRQ tasks.
+ * \brief Performs cache operation on task's context.
+ * \param[in,out] task_ctx Context to be wtb/inv.
+ * \param[in] cmd Cache operation to be performed.
  */
-void arch_free_tasks(void);
+void task_context_cache(void *task_ctx, int cmd);
 
 #endif /* __ARCH_SCHEDULE_TASK_H__ */
 

src/arch/xtensa/include/arch/sof.h

@@ -11,6 +11,10 @@
 #ifndef __ARCH_SOF_H__
 #define __ARCH_SOF_H__
 
+#include <sof/schedule/task.h>
+#include <xtensa/xtruntime-frames.h>
+#include <stdint.h>
+
 /* entry point to main firmware */
 void _ResetVector(void);
 
@@ -28,6 +32,20 @@ static inline void *arch_get_stack_ptr(void)
 	return ptr;
 }
 
+static inline void *arch_get_stack_entry(void)
+{
+	volatile xtos_task_context *task_ctx = task_context_get();
+
+	return task_ctx->stack_base;
+}
+
+static inline uint32_t arch_get_stack_size(void)
+{
+	volatile xtos_task_context *task_ctx = task_context_get();
+
+	return task_ctx->stack_size;
+}
+
 #endif /* __ARCH_SOF_H__ */
 
 #else

src/arch/xtensa/include/xtensa/xtruntime-frames.h

@@ -136,16 +136,30 @@ STRUCT_END(UserFrame)
  *
  * To access the core specific structure from ASM (after threadptr is set):
  * xtos_addr_percore a13, xtos_interrupt_table
- *
- * Access to the core specific structure from C is not supported!
  */
 STRUCT_BEGIN
 STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_enabled)
 STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_intstruct)
 STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_interrupt_table)
 STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_interrupt_mask_table)
+STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_1)
+STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_2)
+STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_3)
+STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_4)
+STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_5)
+STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_saved_sp)
 STRUCT_END(xtos_structures_pointers)
 
+/*
+ * xtos_task_context contains information about currently
+ * executed task
+ */
+STRUCT_BEGIN
+STRUCT_FIELD (UserFrame*,4,TC_,stack_pointer)
+STRUCT_FIELD (void*,4,TC_,stack_base)
+STRUCT_FIELD (long,4,TC_,stack_size)
+STRUCT_END(xtos_task_context)
+
 #if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
 
 

src/arch/xtensa/init.c

@@ -34,43 +34,47 @@ uint32_t lock_dbg_user[DBG_LOCK_USERS] = {0};
 static struct core_context master_core_ctx;
 
 /** \brief Core context pointers for all the cores. */
-struct core_context *core_ctx_ptr[PLATFORM_CORE_COUNT];
+struct core_context *core_ctx_ptr[PLATFORM_CORE_COUNT] = { 0 };
 
-#if CONFIG_SMP
 /** \brief Xtos core data for master core. */
 struct xtos_core_data master_core_data;
 
 /** \brief Xtos core data pointers for all the cores. */
-struct xtos_core_data *core_data_ptr[PLATFORM_CORE_COUNT];
-#endif
+struct xtos_core_data *core_data_ptr[PLATFORM_CORE_COUNT] = { 0 };
 
 /**
  * \brief Initializes core specific data.
  */
 static void initialize_pointers_per_core(void)
 {
-#if CONFIG_SMP
 	int core = cpu_get_id();
-	struct xtos_core_data *core_data = core_data_ptr[core];
+	struct xtos_core_data *core_data;
 	xtos_structures_pointers *p;
 
 	if (core == PLATFORM_MASTER_CORE_ID) {
  master_core_data.thread_data_ptr = &master_core_ctx.td;
  core_ctx_ptr[PLATFORM_MASTER_CORE_ID] = &master_core_ctx;
+ core_data_ptr[PLATFORM_MASTER_CORE_ID] = &master_core_data;
 	}
 
 	cpu_write_threadptr((int)core_ctx_ptr[core]);
 
+	core_data = core_data_ptr[core];
+
 	p = &core_data->thread_data_ptr->xtos_ptrs;
+	p->xtos_saved_sp = &core_data->xtos_saved_sp;
+	p->xtos_stack_for_interrupt_1 = core_data->xtos_stack_for_interrupt_1;
+	p->xtos_stack_for_interrupt_2 = core_data->xtos_stack_for_interrupt_2;
+	p->xtos_stack_for_interrupt_3 = core_data->xtos_stack_for_interrupt_3;
+	p->xtos_stack_for_interrupt_4 = core_data->xtos_stack_for_interrupt_4;
+	p->xtos_stack_for_interrupt_5 = core_data->xtos_stack_for_interrupt_5;
+#if CONFIG_SMP
 	p->xtos_enabled = &core_data->xtos_int_data.xtos_enabled;
 	p->xtos_intstruct = &core_data->xtos_int_data;
 	p->xtos_interrupt_table =
  &core_data->xtos_int_data.xtos_interrupt_table.array[0];
 	p->xtos_interrupt_mask_table =
  &core_data->xtos_int_data.xtos_interrupt_mask_table[0];
-#else
-	core_ctx_ptr[PLATFORM_MASTER_CORE_ID] = &master_core_ctx;
-	cpu_write_threadptr((int)core_ctx_ptr[PLATFORM_MASTER_CORE_ID]);
 #endif
 }
 
@@ -116,7 +120,7 @@ int slave_core_init(struct sof *sof)
 	platform_interrupt_init();
 
 	trace_point(TRACE_BOOT_PLATFORM_SCHED);
-	scheduler_init();
+	scheduler_init(sof);
 
 	/* initialize IDC mechanism */
 	trace_point(TRACE_BOOT_PLATFORM_IDC);
@@ -126,8 +130,8 @@ int slave_core_init(struct sof *sof)
 
 	trace_point(TRACE_BOOT_PLATFORM);
 
-	/* should not return */
-err = do_task_slave_core(sof);
+	/* task initialized in edf_scheduler_init */
+schedule_task(*task_main_get(), 0, UINT64_MAX);
 
 	return err;
 }