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topology2: add deepbuffer to nocodec - #6508
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5d59951CompareRanderWang
commented
Nov 1, 2022
updated. Validated each tplg file and tested sdw on device. |
lgirdwood
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Nov 1, 2022
@RanderWang conflicts. |
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a5ff23bCompareRanderWang
commented
Nov 2, 2022
@lgirdwood conflict was caused by chain dma. please first merge #6514. |
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dcba930CompareRanderWang
commented
Nov 4, 2022
@lgirdwood conflict fixed |
plbossart
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mostly good but this needs serious polish to make it shiny clean
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plbossart
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I'd like the deep-buffer size to be configurable per product. There's no good reason to force everyone to use 100ms upfront.
plbossart
commented
Nov 9, 2022
Actually rebase necessary @RanderWang, looks like there are conflicts? We should also check why we have two TIMEOUTS on 2 out of 3 nocodec test devices. it's a troubling coincidence, isn't it? |
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RanderWang
commented
Nov 15, 2022
SOFCI TEST |
RanderWang
commented
Nov 15, 2022
@lgirdwood all ipc4 test pass now |
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912177eCompareRanderWang
commented
Nov 16, 2022
update deep buffer pcm index to 31 according to topology1 |
plbossart
commented
Nov 16, 2022
except that we didn't follow the convention for all cases in topology1. We should probably update this for compatibility, it has no impact on UCM/users since it's a developer-only config. Can you do this with a follow-up patch @RanderWang ? |
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this looks good but two issues to be aware of before merging @lgirdwood
a) this will conflict with @ranj063 cleanup patch #6592
b) adding a 100ms buffer in the firmware is likely to expose some issues, I would run a daily test on this PR to avoid breaking CI too much.
lgirdwood
commented
Nov 16, 2022
@mengdonglin can we schedule a daily test for this PR as requested by @plbossart ? (can be next week, we can merge the cleanup #6592 first) |
ranj063
commented
Dec 1, 2022
@RanderWang good for rebase now |
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decfc9cCompareranj063
commented
Dec 2, 2022
@RanderWang let us know the results of the daily test with this PR |
RanderWang
commented
Dec 2, 2022
sure, I sent the status to you |
lgirdwood
commented
Dec 2, 2022
@RanderWang@ranj063 pls let me know when ready to merge. |
lgirdwood
commented
Dec 2, 2022
@RanderWang conflicts |
It will be shared by I2S, HDA and SDW platforms Signed-off-by: Rander Wang <rander.wang@intel.com>
Deep buffer is mixed with ssp0 stream. Signed-off-by: Rander Wang <rander.wang@intel.com>
Deep buffer is mixed with Jack out. Signed-off-by: Rander Wang <rander.wang@intel.com>
Deep buffer is mixed with HDA analog. Signed-off-by: Rander Wang <rander.wang@intel.com>
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commented
Dec 5, 2022
@lgirdwood updated. Now it passes all ipc4 test on TGL, but some cases are failed on MTL for power management issue |
marc-hb
commented
Dec 7, 2022
Could this PR cause this recent TGL IPC4 regression? It's the only significant PR that was merged recently. |
I triggered a test plan in ci 18496, check-kmod-load-unload-after-playback passed. Maybe it can result to this bug but it should be in low rate. It will enabled D0i3 if only deepbuffer stream is working. |
marc-hb
commented
Dec 7, 2022
it's a fairly high rate: |
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