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Tools: Testbench: Add IPC4 support#9483
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3292b73be9f07521b55717bf5d3dbbd3865634d19277616b63c3ebc43645e6dfe6b8d8ea2fddae3f13a8c7b090a81295668db545f5b3f6ec088893e2a0284fFile filter
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -534,6 +534,17 @@ static void ipc_compound_msg_done(uint32_t msg_id, int error) | ||
| } | ||
| } | ||
| #if CONFIG_LIBRARY | ||
| /* There is no parallel execution in testbench for scheduler and pipelines, so the result would | ||
| * be always IPC4_FAILURE. Therefore the compound messages handling is simplified. The pipeline | ||
| * triggers will require an explicit scheduler call to get the components to desired state. | ||
| */ | ||
| static int ipc_wait_for_compound_msg(void) | ||
| { | ||
| atomic_set(&msg_data.delayed_reply, 0); | ||
| return IPC4_SUCCESS; | ||
| } | ||
| #else | ||
| static int ipc_wait_for_compound_msg(void) | ||
| { | ||
| int try_count = 30; | ||
| @@ -550,6 +561,7 @@ static int ipc_wait_for_compound_msg(void) | ||
| return IPC4_SUCCESS; | ||
| } | ||
| #endif | ||
| const struct ipc4_pipeline_set_state_data *ipc4_get_pipeline_data_wrapper(void) | ||
| { | ||
| @@ -1603,7 +1615,7 @@ void ipc_cmd(struct ipc_cmd_hdr *_hdr) | ||
| /* FW sends an ipc message to host if request bit is clear */ | ||
| if (in->primary.r.rsp == SOF_IPC4_MESSAGE_DIR_MSG_REQUEST) { | ||
| struct ipc *ipc = ipc_get(); | ||
| struct ipc4_message_reply reply; | ||
| struct ipc4_message_reply reply = {{0}}; | ||
Collaborator There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This kind of stuff could have been in a separate PR btw. CollaboratorAuthor There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I can take it to separate if this review pass takes longer than few days. | ||
| /* Process flow and time stamp for IPC4 msg processed on secondary core : | ||
| * core 0 (primary core) core x (secondary core) | ||
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