Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
cpumipsvhdlmicroprocessorforwardingcomputer-architecturehazard-detectionriscdlxmultiplierbranch-predictordigital-electronicsbtbbht
-
Updated
Dec 10, 2019 - VHDL