Traces, schematics, and general infos about custom chips reverse-engineered from silicon
asicfpgaarcade-gamevideo-gamereverse-engineeringarcadeverilogchipkonamihdlsiliconcpldreprotaitodecapgate-arraystandard-cell
-
Updated
Aug 22, 2026 - Verilog
#
gate-array
Here are 2 public repositories matching this topic...
Logic cell info for gate array and standard cell ASIC reverse-engineering
-
Updated
Jul 2, 2020
Improve this page
Add a description, image, and links to the gate-array topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the gate-array topic, visit your repo's landing page and select "manage topics."