hardware-engineering

ELECTRICAL DAMAGE ⚡🔌 PREVENTION SYSTEM

Automated multi-physics PCB co-design pipeline for thermal-mechanical optimization, transient FEA strain analysis, GDSII layout, and KiCad/Gerber manufacturing generation.

FastAPI + Claude backend for extracting structured data from hardware component datasheets. Built by a hardware engineer • MVP / portfolio.

A Cyber-Physical Sovereign Architecture for Autonomous Grid-Inspection Humanoids: Formal Verification, Lyapunov Dissipation Bounds, and Zero-Trust Sandboxing (IEC 63439 & IEC 62443 Compliant).

Verilog low-latency stream arbitration crossbar with backpressure handling, latency counters, and self-checking verification.

Verilog FPGA orderbook risk gate with exposure limits, sequence integrity, kill switch, and self-checking verification.

Verilog UDP-style market-data feed handler with packet filtering, sequence telemetry, deterministic parsing, and self-checking verification.

Parametric Python & SQLite CAD engine for laser-cut faceplates. Fixes production unit migration drift (cm vs mm), renders vector SVG & ImageMagick PNG previews, and audits keep-out margin compliance.